Methods, systems, and devices for link evaluation for a memory device are described. A memory device may receive signaling over a channel and may identify logic values encoded into the signaling based on sampling the signaling against a reference voltage. The sampling may occur at a reference time within a sampling period. To evaluate a quality (e.g., margin of error) of the channel, the memory device may adjust the reference voltage, the reference time, or both, and either the memory device or the host device may determine whether the memory device is still able to correctly identify logic values encoded into signaling over the channel. In some cases, the channel quality may be evaluated during a refresh cycle or at another opportunistic time for the memory device.

A static random access memory (SRAM) has one or more arrays of memory cells, each array of memory cells activated in columns by a wordline. The activated column of memory cells asserts output data onto a plurality of bitlines coupled to output drivers. The SRAM includes a wordline controller generating a variable pulse width wordline which may be reduced sufficient to introduce memory read errors. Each of a high error rate, medium error rate, low error rate, and error-free rate is associated with a pulse width value generated by the wordline controller. A power consumption tradeoff exists between the wordline pulse width and consumed SRAM power. The wordline controller is thereby able to associate a wordline pulse width to an associated error rate for performing tasks which are insensitive to a high error rate or a medium error rate, which are specific to certain neural network training and inference using various NN data types.

A memory device in which reliability of a clock signal is improved is provided. The memory device comprises a data module including a clock signal generator configured to receive an internal clock signal from a buffer, and to generate a first internal clock signal, a second internal clock signal, a third internal clock signal, and a fourth internal clock signal having different phases, on the basis of the internal clock signal, and a first data signal generator configured to generate a first data signal on the basis of first data and the first internal clock signal, generate a second data signal on the basis of second data and the second internal clock signal, generate a third data signal on the basis of third data and the third internal clock signal, and generate a fourth data signal on the basis of fourth data and the fourth internal clock signal.

Circuitry and methods of operating the same to strobe a DQ signal with a gated DQS signal are described. Some aspects are directed to a gating scheme to selectively pass a received strobe signal such as a DQS strobe signal based on a state of a drive enable (DE) signal in a drive circuit in the ATE, such that edges generated by the drive circuit are prevented from mistakenly strobing a received data signal such as a DQ signal.

An electronic device includes a flag generation circuit and a delay circuit. The flag generation circuit is configured to generate a flag signal, wherein a level of the flag signal changes based on a first internal command. The delay circuit is configured to generate a delay signal by delaying one of an operation signal and the flag signal by a predetermined period according to whether a predetermined operation is performed.

Methods, systems, and devices for clock locking for frame-based communications of memory devices are described. A memory system may include a memory device and a host device. The memory device may receive one or more frames of data from the host device, the one or more frames of data communicated by the host device using a first frame clock. The memory device may generate a second frame clock aligned with the one or more frames on receiving the one or more frames and align one or more operations of the memory device with the second frame clock. In some examples, the host device may receive a second set of frames from the memory device based on transmitting the first set of frames. The host device may align one or more operations of the host device with the second set of frames received from the memory device.

A method of testing a memory device includes steps as follows. Commands that meet a specification of the memory device are used. A random decision is performed on the plurality of commands to generate varied patterns, so that a testing device can test the memory device according to the varied patterns, where each of the varied patterns includes a sequence of one or more commands randomly selected from the plurality of commands.

A semiconductor device including an SRAM capable of sensing a defective memory cell that does not satisfy desired characteristics is provided. The semiconductor device includes a memory cell, a bit line pair being coupled to the memory cell and having a voltage changed towards a power-supply voltage and a ground voltage in accordance with data of the memory cell in a read mode, and a specifying circuit for specifying a bit line out of the bit line pair. In the semiconductor device, a wiring capacitance is coupled to the bit line specified by the specifying circuit and a voltage of the specified bit line is set to a voltage between a power voltage and a ground voltage in a test mode.

A first timing reference signal and a second timing reference signal are sent to a memory device. The second timing reference signal has approximately a quadrature phase relationship with respect to the first timing reference signal. A plurality of serial data patterns are received from the memory device. The transitions of the first timing reference and the second timing reference determining when transitions occur between the bits of the plurality of data patterns. Timing indicators associated with when received transitions occur between the bits of the plurality of data patterns are received from the memory device. The timing indicators are each measured using a single sampler. Based on the timing indicators, a first duty cycle adjustment for the first timing reference signal, a second duty cycle adjustment for the second timing reference signal, and a quadrature phase adjustment are determined and applied.

Memory devices and systems with adjustable through-silicon via (TSV) delay, and associated methods, are disclosed herein. In one embodiment, an apparatus includes a plurality of memory dies and a TSV configured to transmit signals to or receive signals from the plurality of memory dies. The apparatus further includes circuitry coupled to the TSV and configured to introduce propagation delay onto signals transmitted to or received from the TSV. In some embodiments, the apparatus includes additional circuitry configured to activate, deactivate, adjust at least a portion of the circuitry, or any combination thereof, to alter the propagation delay. In this manner, the apparatus can align internal timings of memory dies of the plurality of memory dies.