A degradation detection circuit may include a degradation unit including multiple delay elements driven by a high voltage for degradation. The high voltage for degradation value may be higher than an operation voltage. The degradation unit may be configured to provide a first delayed signal after passing a test signal through the degradation unit, wherein the test signal retains a pulse for a preset time. The degradation detection circuit may include a reference unit including a plurality of delay elements driven by the operation voltage, and configured to provide a second delayed signal after passing the test signal through the reference unit, a delay setting unit configured to provide a third delayed signal by selectively adding delay elements with respect to the second delayed signal, and a delay checking logic configured to detect a delay of the test signal by comparing the first delayed signal and the third delayed signal.

Provided is method and apparatus with memory array programming. A memory apparatus may include a memory array including memory cells, and a memory controller, where the memory controller is configured to configured to repeat, for a plurality of times, a generation of a first present time current error between a first present time current and a first target current, both of a first memory cell, a generation of a second present time current error between a second present time current and a second target current, both of a second memory cell, where a greatest among the first present time current error and the second present time current error is a greatest present time current error, and a programming of a select one of the first and second memory cells that has the greatest present time current error.

An apparatus includes: a master die; one or more slave dies; a ZQ resister between a first node and a second node coupled to a voltage terminal; a ZQ pad coupled to each of the first node of the ZQ resister, the master die and the one or more slave dies; and a calibration channel electrically coupling the master die and the one or more slave dies, the calibration channel configured to communicate signals between the master die and the one or more slave dies for coordinating access to the ZQ pad across the master die and the one or more slave dies.

Automatic memory overclocking, including: increasing a memory frequency setting for a memory module until a memory stability test fails; determining an overclocked memory frequency setting including a highest memory frequency setting passing the memory stability test; and generating a profile including the overclocked memory frequency setting.

A data transceiver device and an operation method are provided. The data transceiver device receives input data and transmits output data. The data transceiver device includes a buffer circuit, a storage circuit, a timing circuit and a control circuit. The buffer circuit is configured to store input data. The storage circuit is configured to store the output data. The timing circuit is configured to generate a time-out signal according to the set time. The control circuit is configured to process the input data to generate the output data, to store the output data in the storage circuit, and to transmit the output data according to an output data threshold value and the time-out signal. The control circuit adjusts the set time and/or the output data threshold value based on an initial condition and the state of the buffer circuit.

There are provided a memory device for supporting a command bus training (CBT) mode and a method of operating the same. The memory device is configured to enter a CBT mode or exit from the CBT mode in response to a logic level of a first data signal, which is not included in second data signals, which are in one-to-one correspondence with command/address signals, which are used to output a CBT pattern in the CBT mode. The memory device is further configured to change a reference voltage value in accordance with a second reference voltage setting code received by terminals associated with the second data signals, to terminate the command/address signals or a pair of data clock signals to a resistance value corresponding to an on-die termination (ODT) code setting stored in a mode register, and to turn off ODT of data signals in the CBT mode.

Disclosed is a device for detecting the margin of a circuit operating at an operating speed. The device includes: a signal generating circuit generating an input signal including predetermined data; a first adjustable delay circuit delaying the input signal by a first delay amount and thereby generating a delayed input signal; a circuit under test performing a predetermined operation based on a predetermined operation timing and thereby generating a to-be-tested signal according to the delayed input signal; a second adjustable delay circuit delaying the to-be-tested signal by a second delay amount and thereby generating a delayed to-be-tested signal; a comparison circuit comparing the data included in the delayed to-be-tested signal with the predetermined data based on the predetermined operation timing and thereby generating a comparison result; and a calibration circuit determining whether the circuit under test passes a speed test according to the comparison result.

A semiconductor apparatus receives a first clock signal and a second clock signal. The semiconductor apparatus configured to perform a training operation internally, the training operation being an operation of internally correcting a phase difference between the first clock signal and the second clock signal by dividing the first clock signal to generate multi-phase signals, detecting phase difference between the second clock signal and the multi-phase signals, and adjusting phases of the multi-phase signals according to a result of the detecting of the phase difference.

Calibration of devices communicating on a shared data bus may improve data integrity on the shared data bus by reducing duty cycle distortion. Duty cycle distortion may be reduced by adjusting timing of a transceiver in a device for communicating on the shared data bus using calibration codes. The calibration codes may be loaded into memory and used to reconfigure the transceiver timing on the shared data bus with reconfiguration occurring within one or more unit-intervals of time. The calibration code may be used, for example, to adjust a PMOS or NMOS trim circuit at the transceiver.

A method and apparatus for continuous write and read operations during memory testing. The method comprises: controlling a signal generator; triggering a write address and a data field operation each memory cycle; triggering a write signal to write to a memory each memory clock cycle; and reading a read address and a read data operation to the memory. An additional embodiment provides an apparatus for advanced memory latency testing. The apparatus includes a data generator trigger in communication with a signal generator and an address generator trigger also in communication with the signal generator.