Methods, systems, and devices for imprint recovery management for memory systems are described. In some cases, memory cells may become imprinted, which may refer to conditions where a cell becomes predisposed toward storing one logic state over another, resistant to being written to a different logic state, or both. Imprinted memory cells may be recovered using a recovery or repair process that may be initiated according to various conditions, detections, or inferences. In some examples, a system may be configured to perform imprint recovery operations that are scaled or selected according to a characterized severity of imprint, an operational mode, environmental conditions, and other factors. Imprint management techniques may increase the robustness, accuracy, or efficiency with which a memory system, or components thereof, can operate in the presence of conditions associated with memory cell imprinting.

A method for performing stutter of dynamic random access memory (DRAM) where a system on a chip (SOC) initiates bursts of requests to the DRAM to fill buffers to allow the DRAM to self-refresh is disclosed. The method includes issuing, by a system management unit (SMU), a ForceZQCal command to the memory controller to initiate the stutter procedure in response to receiving a timeout request, such as an SMU ZQCal timeout request, periodically issuing a power platform threshold (PPT) request, by the SMU, to the memory controller, and sending a ForceZQCal command prior to a PPT request to ensure re-training occurs after ZQ Calibration. The ForceZQCal command issued prior to PPT request may reduce the latency of the stutter. The method may further include issuing a ForceZQCal command prior to each periodic re-training.

Embodiments of the disclosure are drawn to apparatuses methods for checking redundancy information for row addresses prior to performing various refresh operations, such as auto refresh and targeted refresh operations. In some examples, refresh operations may be multi pump refresh operations. In some examples, a targeted refresh operation may be performed prior to an auto refresh operation responsive to a multi pump refresh operation. In some examples, redundancy information for the auto refresh operation may be performed, at least in part, during the targeted refresh operation. In some examples, refresh operations on word lines may be skipped when the redundancy information indicates the word line is defective or unused.

The present disclosure provides a test method and a test apparatus for a semiconductor device. The test method includes: forming a plurality of test values based on a first retention time range and a first step size, and sequentially testing a plurality of memory cells in the semiconductor device based on the plurality of test values in ascending order; determining, during tests corresponding to each test value, a memory cell whose retention time is less than the test value, and recording a position and corresponding test value of the memory cell whose retention time is less than the test value, to form first test data; a similar method is applied to form second test data; and determining, based on the first test data and the second test data, positions and corresponding test values of memory cells whose retention times fail to pass the tests.

The present disclosure relates to a method and apparatus for determining a signal margin (SM) of a memory cell, a storage medium and an electronic device, and relates to the technical field of integrated circuits. The method for determining an SM of a memory cell includes: when the memory cell performs write and read operations, determining a sense signal threshold of the memory cell under an influence of a noise; and determining, based on the sense signal threshold, an actual SM of the memory cell during data reading.

A memory may include multiple rows each coupled to multiple memory cells; a target row classification circuit suitable for classifying, as a target row, a row, among the multiple rows, that is susceptible to data loss as a result of activity of an adjacent row; and a target row signal generation circuit suitable for sequentially activating a target row active signal for activating the target row and a target row precharge signal for precharging the target row in response to a precharge command.

A semiconductor device that has a normal mode of operation and a test mode of operation and can include: a first circuit that generates at least one assist signal having an assist enable logic level in the normal mode of operation, the at least one assist signal alters a read operation or a write operation to a static random access memory (SRAM) cell of the semiconductor device as compared to read or write operations when the assist signal has an assist disable logic level; and the first circuit generates the at least one assist signal having the assist disable logic level in the test mode of operation

A method for determining a leakage current through an inter-gate dielectric structure of a flash memory cell, the flash memory cell including a substrate including a channel region; a floating gate positioned above the channel region and separated from the channel region by a tunnel dielectric layer; a control gate positioned above the floating gate and separated from the floating gate electrode by the inter-gate dielectric structure; the method including programming the flash memory cell into an initial programmed state and applying biasing conditions to the programmed flash memory cell so as to obtain a zero electric field in the tunnel dielectric layer; measuring over time a change in a threshold voltage of the flash memory cell; and determining the leakage current from the change in the threshold voltage.

An apparatus includes a memory circuit that includes a plurality of sub-arrays. The memory circuit is configured to implement a retention mode according to test information indicating voltage sensitivities for the plurality of sub-arrays. The apparatus also includes a voltage control circuit coupled to a power supply node. The voltage control circuit is configured, in response to activation of the retention mode for the plurality of sub-arrays, to generate, based on the test information, at least two different retention voltage levels for different ones of the plurality of sub-arrays. The at least two different retention voltage levels are lower than a power supply voltage level of the power supply node.

A memory may include multiple rows each coupled to multiple memory cells; a target row classification circuit suitable for classifying, as a target row, a row, among the multiple rows, that is susceptible to data loss as a result of activity of an adjacent row; and a target row signal generation circuit suitable for sequentially activating a target row active signal for activating the target row and a target row precharge signal for precharging the target row in response to a precharge command.