A storage system includes a controller part, a data storage part, and a transfer path of a signal that couples these parts. A driver included in the controller part transmits the signal including write data on the basis of a configured parameter, a receiver included in the data storage part receives the signal, and the write data included in the signal is written into a first storage area. The controller part reads the write data from the first storage area, determines whether or not a bit error exists in the write data, changes the parameter when the bit error exists to repeat similar determination and find an appropriate parameter at which the bit error no longer exists.

According to one embodiment, an electromagnet includes a first electromagnet coil having a first portion and a second portion. The first portion of the first electromagnet coil extends in a direction in parallel with a first plane. The second portion of the first electromagnet coil extends in a direction in parallel with a second plane. The first and second planes intersect at a predetermined angle.

According to one embodiment, a magnetic storage device includes a first and a second magnetoresistive effect element, which are disposed in an arrangement pattern including a plurality of arrangement areas, and in each of which a second ferromagnetic layer and a third ferromagnetic layer are antiferromagnetically coupled. A magnetization orientation of the third ferromagnetic layer of the first magnetoresistive effect element is antiparallel to a magnetization orientation of the third ferromagnetic layer of the second magnetoresistive effect element. The first magnetoresistive effect element is disposed in an arrangement area randomly positioned with respect to an arrangement area in which the second magnetoresistive effect element is disposed.

An inter-hamming difference analyzer for a memory array having a plurality of sections is provided. The inter-hamming difference analyzer includes a controller, a storage device and a comparator. The controller is configured to obtain contents of the plurality of sections operating in a first operating condition and a second operating condition. The storage device is configured to store the contents of the plurality of sections corresponding to the first operating condition. The comparator is configured to obtain a plurality of inter-hamming differences of the plurality of sections according to the number of unlike bits between the content of a first section of the plurality of sections corresponding to the second operating condition and the contents of a plurality of sections other than the first section stored in the storage device.

A method, device, and system for improving read performance in frequently changing device temperature conditions through detecting thermal region tags and thermal region outliers in a memory device. A plurality of thermal regions may be configured for the memory device. A first temperature may be measured corresponding to opening a storage block of the memory device for programming. A second temperature may then be measured corresponding to closing the storage block for programming. A range between the first temperature and the second temperature may be determined. The range may span N≥2 of the thermal regions. Finally, the storage block may be assigned to a thermal region that includes the second temperature, on condition that N satisfies a threshold.

A memory apparatus and method of operation is provided. The apparatus has blocks each including non-volatile storage elements. Each of the non-volatile storage elements stores a threshold voltage representative of an element data. The apparatus also includes one or more managing circuits configured to erase at least one of the blocks in an erase operation and program the element data in a program operation. The one or more managing circuits are also configured to proactively identify ones of the blocks as potential bad blocks and selectively apply stress to the ones of the blocks identified as the potential bad blocks and determine whether the potential bad blocks should be retired from the erase and program operations and put in a grown bad block pool or released to a normal block pool used for the erase and program operations based on a judgment after selectively applying the stress.

A method for trimming analog temperature sensors. First, raise a temperature of a temperature sensor to a highest temperature of a qualification temperature range. Then, trim the temperature sensor such that a high temperature code generated by the temperature sensor represents an actual temperature reported by the temperature sensor at the highest temperature. Next, lower the temperature of the temperature sensor to a lowest temperature of the qualification temperature range. Determine a slope error between the high temperature code and a low temperature code generated by the temperature sensor at the lowest temperature. Finally, determine a correction function that compensates for the slope error of measured temperature codes generated by the temperature sensor for temperatures across the qualification temperature range.

A memory device that includes a plurality of non-volatile memory cells and a controller. The controller is configured to erase the plurality of memory cells, program each of the memory cells, and for each of the memory cells, measure a threshold voltage applied to the memory cell corresponding to a target current through the memory cell in a first read operation, re-measure a threshold voltage applied to the memory cell corresponding to the target current through the memory cell in a second read operation, and identify the memory cell as defective if a difference between the measured threshold voltage and the re-measured threshold voltage exceeds a predetermined amount.

A memory device includes a voltage generator that provides a read voltage to a selected word line and provides a pass voltage to a plurality of unselected word lines, and a deterioration level detection circuit. The selected word line and the unselected word lines are connected to a plurality of memory cells. The deterioration level detection circuit detects a deterioration level of memory cells connected to the selected word line based on data of memory cells that receive the read voltage. The memory cells connected to the selected word line and the memory cells that receive the read voltage are included in the plurality of memory cells. The voltage generator changes the pass voltage provided to the unselected word lines based on the deterioration level.

A method of testing a non-volatile memory (NVM) array includes heating the NVM array to a target temperature. While the NVM array is heated to the target temperature, a current distribution is obtained by measuring a plurality of currents of a subset of NVM cells of the NVM array, each NVM cell of the NVM array is programmed to one of a logically high state or a logically low state, and first and second pass/fail (P/F) tests on each NVM cell of the NVM array are performed. A bit error rate is calculated based on the current distribution and the first and second P/F tests.