A device includes a memory and a controller coupled to the memory. The controller is configured to associate a first value of a memory access parameter with a first group indicator. The controller is configured to perform an update operation to determine a second value of the memory access parameter based on first data read from the memory and to generate a first updated value of the memory access parameter. The first updated parameter is associated with the first group indicator and is based on the first value and the second value.

The purpose of the invention is to compensate for the radiation tolerance of a semiconductor memory. An apparatus (10) for compensating for radiation tolerance comprises: a voltage value acquisition unit (11) that acquires a data retention voltage value that is a maximum voltage value at which data is inverted when a power supply voltage of a semiconductor memory having a latch circuit is lowered; a correction value determination unit (12) that determines a voltage correction value on the basis of a difference between the data retention voltage value and a reference voltage value; and a voltage adjustment unit (13) that adjusts at least one among the power supply voltage and a substrate bias voltage by using the voltage correction value. The reference voltage value is set to be equal to or lower than the data retention voltage value that satisfies a required radiation tolerance.

Provided are a flash memory device, a flash memory system, and methods of operating the same. A method of operating a flash memory system includes selecting memory cells of a flash memory in response to an authentication challenge, programming pieces of input data into the selected memory cells, respectively, reading the selected memory cells and generating and storing control information, dividing the selected memory cells into at least one first region memory cell and at least one second region memory cell based on the control information, and setting read values of the at least one first region memory cell and the at least one second region memory cell as a first value and a second value, respectively, and generating an authentication response in the response to the authentication challenge.

The present disclosure relates to an apparatuses and methods for memory management and more particularly to voltage or current detector for a non-volatile memory component that is coupled to a host device or to a System-on-Chip. The memory component includes a memory controller and comprises a voltage or current detector including: a comparator receiving on a voltage input a voltage value Vx; a digital to analog converter coupled to a reference voltage potential and having an output connected to other input of said comparator; a Finite State Machine receiving the output of said comparator and producing digital outputs for the inputs of said memory controller; a current to voltage converter receiving as input a current value Ix to be detected and having an output connected to said Finite State Machine.

To detect deterioration of a correction memory, provided is a semiconductor device including the correction memory that stores therein correction data for correcting a correction target; a correcting section that corrects a detection value of a sensor element, using correction data read from the correction memory; a diagnosing section that diagnoses the correction memory, using the correction data read from the correction memory; and a control section that controls reading conditions used when reading the correction data from the correction memory, wherein the control section causes a first reading condition, used when reading the correction data for correcting a correction target, to differ from a second reading condition, which is used when reading the correction data for the diagnosis.

The present disclosure generally relates to identifying read failures that enhanced post write/read (EPWR) would normally miss. After the last logical word line has been written, additional stress is added to each word line. More specifically, the gate bias channel pass read voltage for all unselected word lines is increased, the gate bias on dummy and selected gate word lines is increased, the gate bias on the selected word line is increased, and a pulse read occurs. The increasing and reading occurs for each word line. Thereafter, EPWR occurs. Due to the increasing and reading for every word line, additional read failures are discovered than would otherwise be discovered with EPWR alone.

A memory device that includes a plurality of non-volatile memory cells and a controller. The controller is configured to erase the plurality of memory cells, program each of the memory cells, and for each of the memory cells, measure a threshold voltage applied to the memory cell corresponding to a target current through the memory cell in a first read operation, re-measure a threshold voltage applied to the memory cell corresponding to the target current through the memory cell in a second read operation, and identify the memory cell as defective if a difference between the measured threshold voltage and the re-measured threshold voltage exceeds a predetermined amount.

A method of operating a memory device comprises generating a target voltage using a pump circuit of the memory device, the target voltage to be applied to a word line or pillar of a memory cell of the memory device; providing an indication of current generated by the pump circuit after the pump circuit output reaches the target voltage; and determining when the current generated by the pump circuit is greater than a specified threshold current and generating a fault indication according to the determination.

A memory device comprises a memory array; a word line driver circuit including a charge pump circuit configured to generate a program voltage target to be applied to a word line to program a memory cell of the memory array, and a control loop to activate the charge pump circuit using a control signal according to a comparison of a pump circuit output voltage to the program voltage target; a sensor circuit that compares a duty cycle of the control signal to a specified duty cycle after the charge pump circuit output reaches the program voltage target, and provides an indication of current generated by the charge pump circuit according to the duty cycle; and logic circuitry that generates a fault indication when the current generated by the charge pump circuit is greater than a specified threshold current.

An integrated circuit includes a primary memory array with cells switchable between first and second states. The circuit also includes sacrificial memory cells; each fabricated to be switchable between the first and second states and associated with at least one row of the primary array. A controller is configured to detect a write operation to a row of the primary array, stress a sacrificial cell associated with the row and detect a failure of the associated sacrificial cell. The sacrificial cells are fabricated to have lower write-cycle endurance than cells of the primary array or are subjected to more stress. Failure of a row of the primary array is predicted based, at least in part, on a detected failure of the associated sacrificial cell.