The present invention discloses a multi-bit-per-cell three-dimensional resistive random-access memory (3D-RRAM.sub.MB). It comprises a plurality of RRAM cells stacked above a semiconductor substrate. Each RRAM cell comprises a RRAM layer, which is switched from a high-resistance state to a low-resistance state during programming. By adjusting the programming current, the programmed RRAMs have different resistances.

Configurable input blocks and output blocks and physical layouts are disclosed for analog neural memory systems that utilize non-volatile memory cells. An input block can be configured to support different numbers of arrays arranged in a horizontal direction, and an output block can be configured to support different numbers of arrays arranged in a vertical direction. Adjustable components are disclosed for use in the configurable input blocks and output blocks. Systems and methods are utilized for compensating for leakage and offset in the input blocks and output blocks the in analog neural memory systems.

Techniques related to monitoring a health of a capacitor array of an SSD are described. In an example, a direct leakage current check is performed by determining voltages of the capacitor array at different times, computing a resistance of the capacitor array based on the voltages, and generating health data for the capacitor array based on the resistance. In another example, an indirect leakage current check is performed by determining at least one of: a number of times a voltage maintaining process is performed within a predefined time duration or a time difference between repeating the voltage maintaining process, comparing the at least one of the number of times or the time difference and a threshold, and generating the health data based on the comparison of the at least one of the number of times or the time difference and the threshold.

A memory storage apparatus and a forming method of a resistive memory device thereof are provided. A test forming voltage is applied to a redundant resistive memory device and a corresponding test current is read. A forming voltage applied to a main memory cell block is determined according to the test forming voltage, the test current, a forming current-voltage characteristic data and a target forming current.

A memory storage apparatus and a forming method of a resistive memory device thereof are provided. A test forming voltage is applied to a redundant resistive memory device and a corresponding test current is read. A forming voltage applied to a main memory cell block is determined according to the test forming voltage, the test current, a forming current-voltage characteristic data and a target forming current.

The present disclosure relates to a device including a built-in-self-test (BIST) circuit configured to run a BIST pattern in a loop mode on a memory which is customized for activity factors corresponding to a programmable number of operations, the BIST circuit being further configured to measure dynamic power on a supply while running the BIST pattern in the loop mode on the memory.

In the present disclosure, it has been appreciated that memory structures, such as static random access memory (SRAM) structures, have feature densities that are extremely high. While this is beneficial in allowing the memory structures to store large amounts of data in a small chip footprint, it is potentially detrimental in that it makes the memory structures more susceptible to leakage current than the other areas of the chip. Accordingly, the present disclosure provides pseudo memory structures which are similar in terms of layout spacing to actual memory structures. However, rather than being used as actual memory structures that store data during operation, these pseudo memory structures are used to characterize leakage current in the design of the IC and/or to characterize the fabrication process used to manufacture the IC.

A cross-bar array includes one or more input row lines, one or more output column lines, one or more resistive processing units (RPUs) coupled at one or more intersections of the input row lines and the output column lines, and a control circuit. A given one of the RPUs includes an analog memory element including a first terminal coupled to a given one of the input row lines and a second terminal coupled to a given one of the output column lines. The analog memory element includes a complementary metal-oxide-semiconductor structure including an n-type field-effect transistor and a p-type field-effect transistor. A gate of the n-type field-effect transistor is coupled to a gate of the p-type field effect transistor to provide a floating gate. The control circuit is configured to read a synaptic weight value of the given RPU by measuring a stored electrical charge of the floating gate.

A cross-bar array includes one or more input row lines, one or more output column lines, one or more resistive processing units (RPUs) coupled at one or more intersections of the input row lines and the output column lines, and a control circuit. A given one of the RPUs includes an analog memory element including a first terminal coupled to a given one of the input row lines and a second terminal coupled to a given one of the output column lines. The analog memory element includes a complementary metal-oxide-semiconductor structure including an n-type field-effect transistor and a p-type field-effect transistor. A gate of the n-type field-effect transistor is coupled to a gate of the p-type field effect transistor to provide a floating gate. The control circuit is configured to read a synaptic weight value of the given RPU by measuring a stored electrical charge of the floating gate.

A memory device can include: a memory array with memory cells arranged as data lines; an interface that receives a read command requesting bytes of data in a consecutively addressed order from an address of a starting byte; a first buffer that stores a first data line from the memory array that includes the starting byte; a second buffer that stores a second data line from the memory array, which is consecutively addressed with respect to the first data line; output circuitry configured to access data from the buffers, and to sequentially output each byte from the starting byte through a highest addressed byte of the first data line, and each byte from a lowest addressed byte of the second data line until the requested data bytes has been output; and a data strobe driver that clocks each byte of data output by a data strobe on the interface.