Multi-Bit-Per-Cell Three-Dimensional Resistive Random-Access Memory (3D-RRAM)

Abstract

The present invention discloses a multi-bit-per-cell three-dimensional resistive random-access memory (3D-RRAM.sub.MB). It comprises a plurality of RRAM cells stacked above a semiconductor substrate. Each RRAM cell comprises a RRAM layer, which is switched from a high-resistance state to a low-resistance state during programming. By adjusting the programming current, the programmed RRAMs have different resistances.

Claims

1. A multi-bit-per-cell three-dimensional resistive random-access memory (3D-RRAM.sub.MB), comprising: a semiconductor substrate including transistors thereon; a RRAM array including a plurality of data RRAM cells stacked above said semiconductor substrate, further comprising: a first dummy RRAM cell in a first state and a first dummy bit line associated therewith, wherein said first dummy RRAM cell is unprogrammed; a second dummy RRAM cell in a second state and a second dummy bit line associated therewith, wherein said second dummy RRAM cell is programmed by a first programming current; and, a third dummy RRAM cell in a third state and a third dummy bit line associated therewith, wherein said third dummy RRAM cell is programmed by a second programming current; a plurality of contact vias coupling said RRAM cells to said semiconductor substrate; a differential amplifier with an input disposed on said semiconductor substrate, wherein said input is coupled with said first and second dummy bit lines during a first measurement, and said input is coupled with said second and third dummy bit lines during a second measurement; wherein said first and second programming currents are different.

2. The 3D-RRAM.sub.MB according to claim 1, wherein said second dummy RRAM cell has a larger resistance than said third dummy RRAM cell.

3. The 3D-RRAM.sub.MB according to claim 1, wherein said first programming current is smaller than said second programming current.

4. A multi-bit-per-cell three-dimensional resistive random-access memory (3D-RRAM.sub.MB), comprising: a semiconductor substrate with transistors thereon; a RRAM array including a plurality of data RRAM cells stacked above said semiconductor substrate, further comprising: a first dummy RRAM cell in a first state and a first dummy bit line associated therewith, wherein said first dummy RRAM cell is unprogrammed; a second dummy RRAM cell in a second state and a second dummy bit line associated therewith, wherein said second dummy RRAM cell is programmed by a first programming current; a third dummy RRAM cell in said second state and a third dummy bit line associated therewith, wherein said third dummy RRAM cell is programmed by a first programming current; a fourth dummy RRAM cell in a third state and a fourth dummy bit line associated therewith, wherein said fourth dummy RRAM cell is programmed by a second programming current; a plurality of contact vias coupling said RRAM array to said semiconductor substrate; a first differential amplifier on said semiconductor substrate, said first differential amplifier having a first input coupled with said first and second dummy bit lines, having a second input coupled with a first selected one of said data RRAM cells; a second differential amplifier on said semiconductor substrate, said second differential amplifier having a third input coupled with said third and fourth dummy bit lines, having a fourth input coupled with a second selected one of said data RRAM cells; wherein said first and second programming currents are different.

5. The 3D-RRAM.sub.MB according to claim 4, wherein said second dummy RRAM cell has a larger resistance than said fourth dummy RRAM cell.

6. The 3D-RRAM.sub.MB according to claim 4, wherein said first programming current is smaller than said second programming current.

7. A multi-bit-per-cell three-dimensional resistive random-access memory (3D-RRAM.sub.MB), comprising: a semiconductor substrate including transistors thereon; a RRAM array stacked above said semiconductor substrate, said RRAM array comprising a plurality of RRAM cells, a plurality of word lines including a data word line, and a plurality of bit lines including a data bit line; a dummy word line in parallel with said data word line; a dummy bit line in parallel with said data bit line; a first dummy RRAM cell disposed at the intersection of said dummy word line and said dummy bit line; a second dummy RRAM cell disposed at the intersection of said data word line and said dummy bit line, wherein said second dummy RRAM cell is unprogrammed; a third dummy RRAM cell disposed at the intersection of said dummy word line and said data bit line, wherein said third dummy RRAM cell is unprogrammed a plurality of contact vias coupling said RRAM cells to said semiconductor substrate; wherein said RRAM cells have N states with N>2, the RRAM cell in different states being programmed by different programming currents.

8. The 3D-RRAM.sub.MB according to claim 7, wherein said RRAM array comprises 2N-2 dummy bit lines.

9. The 3D-RRAM.sub.MB according to claim 7, wherein said RRAM array comprises N dummy bit lines.

10. The 3D-RRAM.sub.MB according to claim 7, wherein all dummy RRAM cells at the intersections of said data word lines and all dummy bit lines in said RRAM array are unprogrammed.

11. The 3D-RRAM.sub.MB according to claim 7, wherein all dummy RRAM cells at the intersections of said dummy word lines and all data bit lines in said RRAM array are unprogrammed.

12. The 3D-RRAM.sub.MB according to claim 7, wherein both voltages on said dummy word line and said data word line are raised during read.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0016] FIG. 1 is a perspective view of a 3D-RRAM.

[0017] FIGS. 2A-2D are cross-sectional views of four preferred 3D-RRAM cells in different states.

[0018] FIG. 3 is a symbol of a RRAM cell.

[0019] FIG. 4A shows a current-voltage (I-V) characteristics of four preferred RRAM cells in different states; FIG. 4B shows a relationship between the resistance of the programmed RRAM and the programming current (R.sub.AF-I.sub.P).

[0020] FIGS. 5A-5C are cross-sectional views of three preferred 3D-RRAM cells;

[0021] FIG. 6A is a circuit block diagram of a preferred RRAM array in the full-read mode; FIG. 6B is its signal timing diagram.

[0022] FIG. 7A is a circuit block diagram of a first preferred RRAM array comprising differential amplifiers; FIGS. 7B-7C are the signal timing diagrams for the reference voltages and the bit-line voltages, respectively.

[0023] FIG. 8A is a circuit block diagram of a second preferred RRAM array comprising a differential amplifier; FIG. 8B is its signal timing diagram.

[0024] FIG. 9 is a preferred 3D-RRAM comprising a dummy word line.

[0025] It should be noted that all the drawings are schematic and not drawn to scale. Relative dimensions and proportions of parts of the device structures in the figures have been shown exaggerated or reduced in size for the sake of clarity and convenience in the drawings. The same reference symbols are generally used to refer to corresponding or similar features in the different embodiments. In FIG. 6A, FIG. 7A, FIG. 8A and FIG. 9, solid dots represent programmed RRAM cells, while open dots represent unprogrammed RRAM cells. The symbol / means a relationship of and or or.

[0026] Throughout the present invention, the phrase on the substrate means the active elements of a circuit are formed on the surface of the substrate, although the interconnects between these active elements are formed above the substrate and do not touch the substrate; the phrase above the substrate means the active elements are formed above the substrate and do not touch the substrate.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0027] Those of ordinary skills in the art will realize that the following description of the present invention is illustrative only and is not intended to be in any way limiting. Other embodiments of the invention will readily suggest themselves to such skilled persons from an examination of the within disclosure.

[0028] Referring now to FIG. 2A-2D, four preferred RRAM cells 1aa-1ad are disclosed. They are in the states: 0, 1, 2, 3, respectively. Each RRAM cell (e.g. 1aa) comprises a top electrode 30a, a bottom electrode 20a, a RRAM layer 22 and a quasi-conductive layer 24. The RRAM layer 22 has high resistance before programming (FIG. 2A), and is switched to low resistance after programming (FIGS. 2B-2D). The quasi-conductive layer 24 has the following properties: its resistance at the read voltage (i.e. the read resistance) is substantially lower than when the applied voltage has a magnitude smaller than or polarity opposite to that of the read voltage. The quasi-conductive layer 24 is also referred to steering element (or, layer), diode element (or, layer), selector, or other names.

[0029] Because the RRAM cell 1aa is unprogrammed, no conductive filament is formed in its RRAM layer 22. On the other hand, because the RRAM cells 1ab-1ad are programmed, conductive filaments 25x-25z of different sizes are formed therein. Among them, the conductive filament 25x of the RRAM cell 1ab is thinnest and has the largest resistance; the conductive filament 25z of the RRAM cell 1ad is thickest and has the lowest resistance; the conductive filaments 25y of the RRAM cell 1ac has an intermediate size and therefore, has an intermediate resistance.

[0030] FIG. 3 is a symbol of a RRAM cell 1. It comprises a RRAM 12 and a diode 14. The RRAM 12 comprises the RRAM layer 22 and its resistance is switched from high to low during programming. The diode 14 comprises the quasi-conductive layer 24 and is broadly interpreted as any two-terminal device whose resistance at the read voltage is substantially lower than when the applied voltage has a magnitude smaller than or polarity opposite to that of the read voltage.

[0031] Referring now to FIGS. 4A-4B, the electrical characteristics of the states 0-3 RRAM cells are disclosed. FIG. 4A shows current-voltage (I-V) characteristics of the states 0-3 RRAM cells. The I-V curve 130 corresponds to a state 0 RRAM cell 1aa; the I-V curve 131 corresponds to a state 1 RRAM cell 1ab; the I-V curve 132 corresponds to a state 2 RRAM cell 1ac; the I-V curve 133 corresponds to a state 3 RRAM cell 1ad. The diode 14 has a turn-on voltage V.sub.on. Once the applied voltage is larger than V.sub.on, the resistance of the diode 14 drops rapidly. At this time, the resistance of the RRAM cell 1 primarily comes from the RRAM layer 12.

[0032] FIG. 4B shows a relationship between the resistance of the programmed RRAM (R.sub.AF) and the programming current (I.sub.P). As R.sub.AF is generally inversely proportional to I.sub.P, the programmed RRAM would have different R.sub.AF by adjusting I.sub.P. For the state 1, the programming current I.sub.P1 is relatively small, thus the RRAM resistance R.sub.1 is relatively large. For the state 3, the programming current I.sub.P3 is relatively large, thus the RRAM resistance R.sub.3 is relatively small. The state 2 is between the states 1 and 3. Overall, I.sub.p1<I.sub.p2<I.sub.p3 leads to R.sub.1>R.sub.2>R.sub.3.

[0033] Referring now to FIGS. 5A-5C, three preferred 3D-RRAM cells 1aa are shown. In the preferred embodiment of FIG. 5A, the bottom electrode (word line) 20a comprises a metallic or highly doped semiconductor material. The top electrode (bit line) 30a comprises a metallic or highly doped semiconductor material. The RRAM layer 22 is a layer of insulating dielectric (e.g. silicon oxide, silicon nitride). The quasi-conductive layer 24 is used to form a diode 14.

[0034] For a semiconductor diode 14, the bottom electrode 20a comprises a P+ semiconductor material, the quasi-conductive layer 24 comprises an N semiconductor material, while the top electrode 30a comprises an N+ semiconductor material. Alternatively, the bottom electrode 20a comprises a metallic material, the quasi-conductive layer 24 comprises a P+/N/N+ diode, while the top electrode 30a comprises another metallic material. It should be apparent to those skilled in the art that other forms of the semiconductor diode can also be used.

[0035] For a Schottky diode 14, the bottom electrode 30a comprises a metallic material, the quasi-conductive layer 24 comprises an N semiconductor material, while the top electrode 30a comprises an N+ semiconductor material. For a ceramic diode 14, the bottom electrode 30a comprises a metallic material, the quasi-conductive layer 24 comprises a ceramic material (e.g. a layer of metal oxide), while the top electrode 30a comprises another metallic material. It should be apparent to those skilled in the art that other forms of the Schottky diode can also be used.

[0036] The preferred embodiment of FIG. 5B is similar to that of FIG. 5A, except that a conductive layer 26 separates the RRAM layer 22 from the quasi-conductive layer 24. The conductive layer 26 preferably comprises at least a metallic material, which minimizes heat damage to the quasi-conductive layer 24 during programming. The preferred embodiment of FIG. 5C is even simpler than those of FIGS. 5A-5B in that it does not comprise a separate quasi-conductive layer. After the RRAM layer 22 is ruptured, a diode is naturally formed at the junction of the top electrode 30a and the bottom electrode 20a. As an example, the bottom electrode 20a comprises a highly doped P+ semiconductor material and the top electrode 20a comprises a highly doped N+ semiconductor material. For those skilled in the art, the RRAM cell 1aa could take other forms.

[0037] To minimize read error due to leaky RRAM cells, the present invention discloses a full-read mode. For the full-read mode, all RRAM cells on a selected word line are read out during a read cycle T. FIGS. 6A-6B discloses a preferred RRAM array 0A in the full-read mode. The RRAM array 0A comprises word lines 20a-20z, bit lines 30a-30z and RRAM cells 1aa-1zz (the numbers in the parenthesis represent the states of the RRAM cells) (FIG. 6A). The preferred embodiment further comprises a single-ended amplifier 58S. The read cycle T includes two read phases: a pre-charge phase t.sub.pre and a read-out phase t.sub.R (FIG. 6B). During the pre-charge phase t.sub.pre, all address lines 20a-20z, 30a-30z in the RRAM array 0A are charged to an input bias voltage V.sub.i of the amplifier 58S.

[0038] During the read-out phase t.sub.R, all bit lines 30a-30z are floating. Based on the row address 52A, the row decoder 52 raises the voltage on a selected word line 20a to the read voltage V.sub.R, while voltage on unselected word lines 20b-20z remains at the input bias voltage V.sub.i. After this, the selected word line 20a starts to charge the bit lines 30a-30z through the RRAM cells 1aa-1az and the voltages on the bit lines 30a-30z begin to rise. At this time, the voltage on each bit line is sent to the amplifier 58S by rotating the column address 54A. For each column address 54A, the column decoder 54 selects a bit line (e.g. 30b) and sends its voltage Vb to the input 51 of the amplifier 58S. When the value of the voltage V.sub.b exceeds the threshold voltage V.sub.T of the amplifier 58S, the output 55 is toggled. By measuring the toggling time, the state of each RRAM cell (e.g. the RRAM cell 1ab at the intersection of the selected word line 20a and the selected bit line 30b) can be determined.

[0039] During the above measurement, because the V.sub.T of the amplifier 58S is relatively small (0.1V or smaller), the voltage changes delta(V) on the bit lines 30a-30z are small. The largest voltage change delta(V).sub.maxN*V.sub.T is far less than the read voltage V.sub.R. As long as the I-V characteristics of the RRAM cell satisfies I(V.sub.R)>>I(N*V.sub.T), the 3D-RRAM.sub.MB would work properly even with leaky RRAM cells.

[0040] To minimize read error due to external interferences, the present invention further discloses differential amplifiers for measuring the states of the RRAM cells. FIGS. 7A-C disclose a first preferred RRAM array 0A with differential amplifiers. In addition to the regular bit line 30a-30z and RRAM cells 1aa-1zz (FIG. 6A), the preferred RRAM array 0A further comprises dummy bit lines 31a-31f and dummy RRAM cells 1a0-1z5 (FIG. 7A). For clarity, the regular bit line 30a-30z are referred to as data bit lines, while the regular RRAM cells 1aa-1zz are referred to as data RRAM cells. The dummy bit lines 31a-31f form a dummy bit-line set 30DY, while the data bit lines 30a-30z form a data bit-line set 30DT.

[0041] This preferred embodiment further comprises N-1(in this case, =3) differential amplifiers 58a-58c (FIG. 7A). All differential amplifiers 58a-58c comprise two inputs: first inputs are the bit-line voltage V.sub.b from a data RRAM cell (i.e. the RRAM cell stores data), while second inputs are the reference voltages V.sub.ref,1-V.sub.ref,3. For example, the reference voltage for the differential amplifier 58a is V.sub.ref,1(V.sub.0 +V.sub.1)/2; the reference voltage for the differential amplifier 58b is V.sub.ref,2(V.sub.1+V.sub.2)/2; and, the reference voltage for the differential amplifier 58c is V.sub.ref,3(V.sub.2+V.sub.3)/2. As used herein, V.sub.i(i=0, 1, 2, or 3) is the voltage on the associated bit line when reading out a state I RRAM cell.

[0042] To generate these reference voltages V.sub.ref,1-V.sub.ref,3, the RRAM array 0A uses 2N-2 (in this case, =6) dummy bit lines 31a-31f. Each word line (e.g. 20a) is associated with 2N-2 (in this case, =6) dummy RRAM cells (e.g. 1a0-1a5). Like the data RRAM cells 1aa-1az, the dummy RRAM cells 1a0-1a5 have N states. For example, the dummy RRAM cells 1aa0-1a5 on the word line 20a are in the states 0, 1, 1, 2, 2, 3, 3, respectively (FIG. 7A). The reference voltage V.sub.ref,1 on the second input 53a of the amplifier 58a is generated by shorting the dummy bit lines 31a (coupled with a 0 dummy RRAM cell 1a0) and 31b (coupled with a 1 dummy RRAM cell 1a1). Namely, V.sub.ref,1=(V.sub.31a+V.sub.31b)/2=(V.sub.0+V.sub.1)/2 (FIG. 7B). The reference voltage V.sub.ref,2 on the second input 53b of the amplifier 58b is generated by shorting the dummy bit lines 31c (coupled with a 1 dummy RRAM cell 1a2) and 31d (coupled with a 2 dummy RRAM cell 1a3). Namely, V.sub.ref,2=(V.sub.31c+V.sub.31d)/2=(V.sub.1+V.sub.2)/2. The reference voltage V.sub.ref,3 on the second input 53c of the amplifier 58c is generated by shorting the dummy bit lines 31e (coupled with a 2 dummy RRAM cell 1a4) and 31f (coupled with a 3 dummy RRAM cell 1a5). Namely, V.sub.ref,3=(V.sub.31e+V.sub.31f)/2=(V.sub.2+V.sub.3)/2.

[0043] To determine the state of a selected data RRAM cell, N-1 measurements are taken concurrently at the N-1 amplifiers 58a-58c. The data RRAM cell is in the state k if V.sub.ref,k-1<V.sub.b<V.sub.ref,k (k=1, 2, . . . N-1). For example, to measure the state of the data RRAM cell 1ab, the column decoder 54 sends the voltage on the bit line 30b to the first inputs of all amplifiers 58a-58c. The amplifiers 58a-58c make three measurements concurrently (FIG. 7C). As the data RRAM cell lab is in the state 2, the bit-line voltage V.sub.b on the first input 51 is larger than the reference voltages V.sub.ref,1, V.sub.ref,2 on the second inputs 53a, 53b of the amplifiers 58a, 58b, respectively. However, V.sub.b is smaller than V.sub.ref,3 on the second input 53c of the amplifier 58c. Thus, the outputs 55a-55c of the amplifiers 58a-58c are high, high, low. Accordingly, the state of the data RRAM cell 1ab can be determined.

[0044] FIGS. 8A-8B discloses a second preferred RRAM array 0A comprising an amplifier. Instead of three amplifiers 58a-58c (FIG. 7A), it uses a single amplifier 58D (FIG. 8A). The first input of the amplifier 58D is the bit-line voltage V.sub.b of a selected data RRAM cell, while the second input is a selected reference voltage V.sub.ref. This preferred embodiment uses fewer dummy bit lines and dummy RRAM cells than FIG. 7A. The RRAM array 0A comprises only N (in this case, =4) dummy bit lines 32a-32d and each word line (e.g. 20a) is coupled with N dummy RRAM cells (e.g. 1a0-1a3). Like the data RRAM cells 1aa-1az, the dummy RRAM cells 1a0-1a3 have N states. For example, the dummy RRAM cells 1aa0-1a3 on the word line 20a are in the states 0, 1, 2, 3, respectively (FIG. 8A). Adjacent dummy bit lines (e.g. 32a, 32b) are coupled through a pair of pass transistors (e.g. 56a1, 56a2), which is controlled by a control signal 56a. An appropriate reference voltage V.sub.ref is generated by asserting the corresponding control signals. For example, by asserting the control signal 56a, the passing transistors 56a1, 56a2 is turned on and the reference voltage V.sub.ref is equal to the average of the voltages on the dummy bit lines 32a, 32b. Namely, V.sub.ref=V.sub.32a+V.sub.32b=(V.sub.0+V.sub.1)/2.

[0045] To determine the state of a selected data RRAM cell, N-1 measurements are taken sequentially at the amplifier 58D (FIG. 8B). The RRAM cell is in the state k if V.sub.ref,k-1<V.sub.b<V.sub.ref,k (k=1, 2, . . . N-1). For example, to determine the state of the data RRAM cell lab, the column decoder 54 sends the voltage V.sub.b (=V.sub.2) on the bit line 30b to the first input 51 of the amplifier 58D. Three sequential measurements are taken. During the first measurement T.sub.1, the control signal 56a is asserted to turn on the pass transistors 56a1, 56a2. The reference voltage V.sub.ref on the second input 53 of the amplifier 58D is V.sub.ref=(V.sub.0+V.sub.1)/2. As V.sub.ref<V.sub.b, the output 55 of the amplifier 58D is high. Similarly, during the second measurement T.sub.2, by turning on the pass transistors 56b1, 56b2, the output 55 of the amplifier 58D stays high as V.sub.ref=(V.sub.1+V.sub.2)/2<V.sub.b; during the third measurement T.sub.3, by turning on the pass transistors 56c1, 56c2, the output 55 of the amplifier 58D turns low as V.sub.ref=(V.sub.2+V.sub.3)/2>V.sub.b. By analyzing the results from three measurements T.sub.1-T.sub.3, the state of the data RRAM cell 1ab can be determined.

[0046] In the preferred embodiments of FIGS. 6A-8B, the row decoder 52, the column decoder 54 and the amplifier 58S, 58a-58c, 58D are formed on the substrate 0 and are a portion of the substrate circuit 0K. The RRAM array 0A is stacked above the substrate circuit 0K and covers at least a portion thereof. The 3D-RRAM.sub.MB has a small die size and a low die cost.

[0047] All dummy RRAM cells need to be pre-programmed before shipping. During pre-programming, the resistances of the dummy RRAM cells need to be adjusted precisely. For the preferred embodiment of FIG. 7A (or, FIG. 8A), each word line 20a is associated with 2N-2 (or, N) dummy RRAM cells. The total number of the dummy RRAM cells in the RRAM array 0A (with M data word lines and N data bit lines) is (2N-2)*M (or, N*M). Pre-programming all of them is time consuming and costly. To reduce the pre-programming time, the present invention further discloses a dummy word line. FIG. 9 discloses a preferred RRAM array 0A comprising a dummy word line 20D. In addition to the data word lines 20a, 20b, . . . 20y, 20z, the preferred RRAM array 0A comprises a dummy word line 20D. The pre-programming is only carried out to the dummy RRAM cells 1D1-1D5 located at the intersections of the dummy word line 20D and the dummy bit lines 31b-31f. Because majority of the dummy RRAM cells (e.g. 1a0-1b5, 1y0-1z5) do not need pre-programming, the pre-programming time is significantly reduced.

[0048] During read, both voltages on the selected data word line (e.g. 20a) and the dummy word line 20D are raised to V.sub.R. Because the dummy RRAM cells 1Da-1Dz at the intersections of the dummy word line 20D and the data bit lines 30a-30z are un-programmed, the voltage rise on the dummy word line 20D would not affect the signals on the data bit lines 30a-30z. Moreover, because the dummy RRAM cells 1a0-1a5 at the intersections of the data word line 20a and the dummy bit lines 31a-31f are un-programmed, the voltage rise on the data word line 20a would not affect the signals on the dummy bit lines 31a-31f, either. Accordingly, the operation of this preferred embodiment is similar to those in FIGS. 7A-8B.

[0049] In the preferred embodiments of FIGS. 7A-9, to manufacture high-quality dummy RRAM cells, all dummy word line, dummy bit lines and dummy RRAM cells are preferably formed in the middle of the RRAM array 0A. For example, the dummy word line 20D is formed in the middle of the RRAM array 0A, so are the dummy bit lines 31a-31f.

[0050] Although examples disclosed in these figures are horizontal 3D-RRAM (i.e. the RRAM memory levels 100, 200 are horizontal), the inventive spirit can be extended to vertical 3D-RRAM (i.e. the RRAM memory strings are vertical to the substrate).

[0051] While illustrative embodiments have been shown and described, it would be apparent to those skilled in the art that many more modifications than that have been mentioned above are possible without departing from the inventive concepts set forth therein. For example, beside N=4 (i.e. each RRAM cell stores two bits), the present invention can be extended to N=8 (i.e. each RRAM cell stores three bits) or more. The invention, therefore, is not to be limited except in the spirit of the appended claims.