Methods, systems, and devices for leakage source detection are described. In some cases, a testing device may scan a first set of access lines of a memory die that have a first length and a second set of access lines of the memory die that have a second length different than the first length. The testing device may determine a first error rate associated with the first set of access lines and a second error rate associated with the second set of access lines. The testing device may categorize a performance of the memory die based on the first and second error rates. In some cases, the testing device may determine a third error rate associated with a type of error based on the first and second error rates and may categorize the performance of the memory die based on the third error rate.

A memory circuit includes a first driver circuit, a first column of memory cells coupled to the first driver circuit, a first current source, a tracking circuit configured to track a leakage current of the first column of memory cells, and a footer circuit coupled to the first column of memory cells, the first current source and the tracking circuit.

In the present disclosure, it has been appreciated that memory structures, such as static random access memory (SRAM) structures, have feature densities that are extremely high. While this is beneficial in allowing the memory structures to store large amounts of data in a small chip footprint, it is potentially detrimental in that it makes the memory structures more susceptible to leakage current than the other areas of the chip. Accordingly, the present disclosure provides pseudo memory structures which are similar in terms of layout spacing to actual memory structures. However, rather than being used as actual memory structures that store data during operation, these pseudo memory structures are used to characterize leakage current in the design of the IC and/or to characterize the fabrication process used to manufacture the IC.

Methods of optimizing the placement of memories in a memory device including a substrate and an electrical component, and associated devices and systems, are disclosed herein. A representative method includes first testing the memories to determine at least one parameter for each of the memories indicating an ability of the memory to process signals from the electrical component. The method can further include labeling each memory with a label based on the parameter, the labels including at least a first label and a second label. The first label can indicate that the memories with the first label are better able to process signals from the electrical component than the memories with the second label. The method can further include electrically coupling the memories to the substrate such that the memories with the second label are positioned closer to the electrical component than the memories with the first label.

A leakage detection circuit may include: a comparison circuit configured to compare an input voltage, which changes based on the level of an operation voltage node, to a reference voltage and configured to output a detection signal; and a state decision circuit configured to determine a count value that corresponds to a determination period based on the detection signal and configured to output leakage state information based on the count value.

A non-volatile memory device includes: one or more memory blocks including a plurality of memory cells connected to a plurality of word lines, and a plurality of memory cell strings; a page buffer unit; one or more pass units including a plurality of pass transistors that may supply operation voltages to the plurality of word lines; one or more monitoring units including one or more monitoring pass transistors connected to the plurality of pass transistors; a voltage generator that may supply activation voltages to a first pass transistor, in which a leakage current is to be measured, and to the one or more monitoring pass transistors; and a control logic that may control the voltage generator to generate the activation voltages by using a voltage control signal and detect the leakage current based on monitoring voltages output from the one or more monitoring pass transistors.

Devices, systems and methods for adaptively controlling a reset current of a memory cell are described. A system comprises: a mirror circuit with one branch coupled with a top electrode of the memory cell and the other branch coupled with one end of a resistive reference, and wherein a bottom electrode of the memory cell is coupled to a reference potential, the other end of the resistive reference is provided with a first electric potential; a control circuit; and a feedback circuit for feeding an electric potential to the top electrode of the memory cell.

A method for determining a leakage current through an inter-gate dielectric structure of a flash memory cell, the flash memory cell including a substrate including a channel region; a floating gate positioned above the channel region and separated from the channel region by a tunnel dielectric layer; a control gate positioned above the floating gate and separated from the floating gate electrode by the inter-gate dielectric structure; the method including programming the flash memory cell into an initial programmed state and applying biasing conditions to the programmed flash memory cell so as to obtain a zero electric field in the tunnel dielectric layer; measuring over time a change in a threshold voltage of the flash memory cell; and determining the leakage current from the change in the threshold voltage.

Methods, systems, techniques, and devices for operating a ferroelectric memory cell or cells are described. Groups of cells may be operated in different ways depending, for example, on a relationship between cell plates of the group of cells. Cells may be selected in pairs in order to accommodate an electric current relationship, such as a short, between cells that make up the pair. Cells may be arranged in cell plate groups, and a pair of cells may include a first cell plate from one cell plate group and a second cell plate from the same cell plate group or from another, adjacent cell plate group. So a pair of cell plates may include cell plates from different cell plate groups. The first and second cell plates may be selected as a pair or a group based at least in part on the electric current relationship between the cell plates.

An integrated circuit device includes a plurality of cells or modules. Each respective one of the cells or modules consumes leakage power, and the amount of leakage power consumed by a respective one of the cells or modules varies depending on states of its inputs. Scan-chain circuitry is configured to propagate through the integrated circuit device, on entry of the integrated circuit device to a low-power mode, a scan-chain pattern created in advance, to apply, to each respective cell or module in the low-power mode, a set of inputs that results in a respective low-power state with reduced leakage power. Creating the scan chain pattern includes identifying respective ones of the cells or modules as having the highest leakage power consumption, and a respective combination of inputs to place each of those the cells or modules in a respective low-power state.