A memory device includes a plurality of memory dies, each memory die of the plurality of memory dies comprising a memory array and a power management component, operatively coupled with the memory array. The power management component sends a test value to one or more other power management components on one or more other memory dies of the plurality of memory dies and receives one or more other test values from the one or more other power management components. The power management component compares the test value and the one or more other test values to a set of expected values, and responsive to the test value and the one or more other test values matching the set of expected values, determines that signal connections between the power management component and the one or more other power management components are functional.

An apparatus has an array of memory cells and a controller coupled to the array. The controller is configured to track a sub-threshold leakage current through a number of memory cells of the array and determine a threshold voltage based on the sub-threshold leakage current.

A resistive memory device and a reliability enhancement method thereof are provided. The reliability enhancement method includes the following steps. A forming operation is performed on a plurality of memory cells. The formed memory cells are read to respectively obtain a plurality of formed currents. A reference current is set according to a statistic value of the formed currents. A setting operation is performed on the memory cells. A ratio between a set current of each of the memory cells and the reference current is calculated, and a physical status of each of the memory cells is judged according to the ratio. It is determined whether to perform a fix operation of each of the memory cells or not according to physical status.

The present disclosure relates to an apparatus, and a method for memory management and more a memory device structured with internal analogic measurement mode features. The memory device includes memory component having a memory array, a memory controller coupled to the memory component, a JTAG interface in the memory controller, voltage and current reference generators, and an analogic measurement block driven by the JTAG interface.

A method and apparatus for intensifying current leakage between adjacent memory cells includes that: a write operation is performed on a memory array, to form a column strip test pattern, the column strip test pattern being formed by arranging low-level memory cells and high-level memory cells in columns, and N columns of high-level memory cells being present between two adjacent columns of low-level memory cells, N≥2; and voltage adjustment is performed on the low-level memory cells and the high-level memory cells, to increase potential differences between the low-level memory cells and the high-level memory cells.

A method and a device for testing a memory chip are provided. The method includes: writing test data into memory cells of a memory chip to-be-tested; reading stored data from the memory cells; and generating a test result of the memory chip to-be-tested according to the test data and the stored data; a word line turn-on voltage tested in the memory chip to-be-tested being greater than a standard bit line and word line turn-on voltage of the memory chip to-be-tested, and/or a sense amplification time tested in the memory chip to-be-tested being greater than a standard sense amplification time of the memory chip to-be-tested.

The present disclosure relates to an apparatus, and a method for memory management and more a memory device structured with internal analogic measurement mode features. The memory device includes memory component having a memory array, a memory controller coupled to the memory component, a JTAG interface in the memory controller, voltage and current reference generators, and an analogic measurement block driven by the JTAG interface.

A method of operating a nonvolatile memory device which includes at least one memory block is provided. The method includes providing a plurality of word-lines with a voltage during a word-line set-up period, precharging a plurality of driving lines with a voltage during a word-line development period, detecting a voltage drop of a sensing node during a sensing period, and detecting leakage based on the voltage drop.

A system for testing memory includes logic that is configured to perform various normal memory operations (e.g., erase, read and write operations) on a memory device and to determine operational parameters associated with the memory operations. As an example, the amount of time to perform one or more memory operations may be measured, a number of errors resulting from the memory operations may be determined, or a number of memory cells storing noisy bits may be identified. One or more of the operational parameters may then be analyzed to determine whether they are in a range expected for counterfeit or defective memory. If so, the logic determines that the memory under test is counterfeit or defective and provides a notification about such determination.

Some examples relate to a method. In this method, a metal isolation test circuit, which is disposed on a semiconductor substrate, is received. The metal isolation test circuit includes a plurality of transistors and an interconnect structure coupled to the plurality of transistors. The interconnect structure includes a plurality of pins. A first voltage bias is applied across first and second pins of the plurality of pins, and a first leakage current is measured while the first voltage bias is applied. A process or a design rule by which the metal isolation test circuit is made is characterized based on the first leakage current.