A method of writing data into a memory device is disclosed. The method comprises utilizing a pipeline to process write operations of a first plurality of data words addressed to a memory bank and writing a second plurality of data words and associated memory addresses into an error buffer. The method also comprises monitoring a first counter value which tracks a number of write 1 errors and a second counter value which tracks a number of write 0 errors in the memory bank. Further, the method comprises determining if the first counter value and the second counter value have exceeded a predetermined threshold. Responsive to a determination that the first counter value has exceeded the predetermined threshold increasing a write 1 voltage of the memory bank, and, further, responsive to a determination that the second counter value has exceeded the predetermined threshold increasing a write 0 voltage of the memory bank.

In a method of reading initialization information from a non-volatile memory device, when power-up is detected, the non-volatile memory device divides a source voltage to generate a low read pass voltage which is to be provided to unselected word lines in an initialization information read operation. The low read pass voltage is set as at least one voltage between a ground voltage and the source voltage. The non-volatile memory device allows the source voltage not to be pumped in the initialization information read operation, based on the power-up. In the initialization information read operation, the non-volatile memory device provides the low read pass voltage to the unselected word lines and provides a read voltage to a selected word line to read initialization information stored in the memory cells.

A method for managing a storage medium in a storage device is provided. The method includes detecting whether there is a problematic storage block in a data storage area of the storage medium, wherein the problematic storage block is a storage block whose health degree is less than a preset value, wherein the health degree is used to measure performance of a storage block in the storage medium and is in direct proportion to the performance of the storage block; and replacing the problematic storage block with a replacement storage block in a replacement area of the storage medium when the problematic storage block is detected, wherein a health degree of a storage block in the data storage area is greater than a health degree of a storage block in the replacement area.

A memory system includes: a memory device; a run-time bad block detector suitable for storing information of super memory blocks, each including a run-time bad block, in a bad list; a bit-map manager suitable for generating a bit-map representing integrity information of memory blocks in each of the super memory blocks; a short super block manager suitable for designating, among the super memory blocks, a super memory block having a number of run-time bad blocks less than or equal to a threshold as a short super memory block based on the bad list and the bit-map, whenever a logical unit configuration command is received from a host; and a processor suitable for controlling the memory device to simultaneously access normal blocks among the memory blocks forming the designated short super memory block and to perform a normal operation, based on the bit-map.

Apparatuses and methods for latching redundancy repair addresses at a memory are disclosed. An example apparatus includes block of memory including primary memory and a plurality of redundant memory units and repair logic. The repair logic including a plurality of repair blocks. A repair block of the plurality of repair blocks is configured to receive a set of repair address bits associated with a memory address for defective memory of the block of memory and to latch the set of repair address bits at a respective set of latches. The repair block is further configured to, in response to receipt of a memory access request corresponding to the set of repair address bits latched at the repair block, redirecting the memory access request to a redundant memory unit associated with the repair block.

In a method of reading initialization information from a non-volatile memory device, when power-up is detected, the non-volatile memory device divides a source voltage to generate a low read pass voltage which is to be provided to unselected word lines in an initialization information read operation. The low read pass voltage is set as at least one voltage between a ground voltage and the source voltage. The non-volatile memory device allows the source voltage not to be pumped in the initialization information read operation, based on the power-up. In the initialization information read operation, the non-volatile memory device provides the low read pass voltage to the unselected word lines and provides a read voltage to a selected word line to read initialization information stored in the memory cells.

Memory devices, systems including memory devices, and methods of operating memory devices in which redundancy match is disabled to permit activating more word lines in parallel during refresh operations to increase a refresh rate of memory cells in a memory array. In one embodiment, a memory device is provided, comprising a memory array including a plurality of word lines arranged in a plurality of memory banks. The memory device further comprises circuitry configured to (i) store a value indicating one or more addresses corresponding to word lines in the plurality of word lines, (ii) disable redundancy match, (iii) activate one or more first word lines in the memory array corresponding to the one or more addresses indicated by the value to refresh first data stored in the memory array, and (iv) update the value based at least in part on activating the one or more first word lines.

A memory module is disclosed that includes a substrate, a memory device that outputs read data, and a buffer. The buffer has a primary interface for transferring the read data to a memory controller and a secondary interface coupled to the memory device to receive the read data. The buffer includes error logic to identify an error in the received read data and to identify a storage cell location in the memory device associated with the error. Repair logic maps a replacement storage element as a substitute storage element for the storage cell location associated with the error.

Provided herein may be a storage device having improved operating speed and a method of operating the same. The storage device may include a memory controller configured to control the plurality of dies, each including two or more planes. The memory controller may include a reserved block information storage unit configured to store reserved block information that is information related to reserved blocks included in the plurality of dies; and a bad block management control unit configured to set, when a bad block occurs among memory blocks respectively included in the plurality of dies, a reserved block to replace the bad block depending on whether any one of available reserved blocks are included in a plane to which the bad block belongs, among the two or more planes included in a die including the bad block, based on the reserved block information.

The present disclosure includes methods and apparatuses for read cache memory. One apparatus includes a read cache memory apparatus comprising a first DRAM array, a first and a second NAND array, and a controller configured to manage movement of data between the DRAM array and the first NAND array, and between the first NAND array and the second NAND array.