Devices, methods, and systems for managing temperature dependent failures in a memory device. An erase failure of a memory block is detected, and marked as a grown bad block if the memory device temperature is below a threshold temperature. If the temperature exceeds the threshold temperature, it is determined whether memory cells of the block exceed a first threshold voltage. If the memory cells of the block exceed the first threshold voltage, the block is marked as a potential grown bad block. If the memory cells of the block are below the first threshold voltage, it is determined whether a number of the memory cells of the block exceed a second threshold voltage. If the memory cells of the block are below the second threshold, the block is programmed. If the memory cells of the block exceed the second threshold, the block is marked for error correction and programmed.

Devices, methods, and systems for managing temperature dependent failures in a memory device. An erase failure of a memory block is detected, and marked as a grown bad block if the memory device temperature is below a threshold temperature. If the temperature exceeds the threshold temperature, it is determined whether memory cells of the block exceed a first threshold voltage. If the memory cells of the block exceed the first threshold voltage, the block is marked as a potential grown bad block. If the memory cells of the block are below the first threshold voltage, it is determined whether a number of the memory cells of the block exceed a second threshold voltage. If the memory cells of the block are below the second threshold, the block is programmed. If the memory cells of the block exceed the second threshold, the block is marked for error correction and programmed.

Addresses of accessed word lines are stored. Data related to victim word lines associated with the accessed word line are also stored. The victim word lines may have data stored in relation to multiple accessed word lines. The data related to the victim word lines is adjusted when the victim word line is refreshed during a targeted refresh operation or an auto-refresh operation. The data related to the victim word lines is adjusted when the victim word line is accessed during a memory access operation.

A method of protecting a DRAM memory device from the row hammer effect includes the memory device comprising a plurality of banks composed of memory rows, the method being implemented by at least one logic prevention device configured to respectively associate contiguous sections of rows of a bank with sub-banks and to execute, on each activation of a row of a sub-bank (b) of the memory, an increment step of a required number of preventive refreshments (REFRESH_ACC; REFRESH_ACC/PARAM_D) of the sub-bank (b) using an activation threshold (PARAM_D) of the sub-bank (b). The prevention logic is also configured to execute a preventive refresh sequence of the sub-banks according to their required number of preventive refreshes. A DRAM memory device, a buffer circuit or a controller of such a memory may comprise the logic for preventing the row hammer effect.

An apparatus includes a first word line, a second word line and a control. The second word line is contiguous to the first word line. The control circuit includes a first defective address storing circuit and a first detection circuit. The first defective address storing circuit stores first enable information along with first defective address. The first enable information indicates whether or not the second word line is functional. The first detection circuit provides a first signal when the first word line is accessed. The first signal indicates whether or not the second word line is functional. The control circuit activates the second word line when the first signal indicates that the second word line is functional and does not activate the second word line when the first signal indicates that the second word line is not functional.

A memory module includes a first channel of first data memories and a first error correction code (ECC) memory, and a second channel of second data memories and a second ECC memory. Each first data memory transmits a corresponding first data set of first data sets with a memory controller. Each first data set corresponds to a burst length. Each second data memory transmits a corresponding second data set of the second data sets with the memory controller. Each second data set corresponds to the burst length. The first ECC memory stores first sub parity data for detecting at least one error in all of the first data sets stored in the first data memories. The second ECC memory stores second sub parity data for detecting at least one error in all of the second data sets stored in the second data memories.

Apparatuses and methods for targeted row refreshes are disclosed herein. In an example apparatus, a predecoder receives a target row address and determines whether a target row of memory associated with the target row address is a primary or a redundant row of memory. The predecoder is further configured to cause one or more rows of memory physically adjacent the primary row of memory to be refreshed if the primary row is the target row or one or more rows of memory physically adjacent the redundant row of memory to be refreshed if the redundant row of memory is the target row of memory.

Memory devices, systems including memory devices, and methods of operating memory devices in which redundancy match is disabled to permit activating more word lines in parallel during refresh operations to increase a refresh rate of memory cells in a memory array. In one embodiment, a memory device is provided, comprising a memory array including a plurality of word lines arranged in a plurality of memory banks. The memory device further comprises circuitry configured to (i) store a value indicating one or more addresses corresponding to word lines in the plurality of word lines, (ii) disable redundancy match, (iii) activate one or more first word lines in the memory array corresponding to the one or more addresses indicated by the value to refresh first data stored in the memory array, and (iv) update the value based at least in part on activating the one or more first word lines.

A storage device including repairable volatile memory and a method of operating the same are provided. The storage device includes a non-volatile memory storing user data, a volatile memory buffering the user data and performing a test for detecting a defective cell on a volatile cell array at an idle time of the storage device, and a controller controlling the volatile memory to perform the test at an idle time and storing test information including a test result or a test history in the non-volatile memory.

An apparatus may include an address counter to provide first address information and second address information. The first address information may include a first number of bits and the second address information may include a second number of bits that is smaller than the first number of bits. The address counter may perform a first updating operation. The first updating operation being such that the first address information is updated from a first initial value to a first final value. The address counter may also perform a second updating operation, the second updating operation being such that the second address information is updated from a second initial value to a second final value. In addition, the address counter may also perform the second updating operation at least twice per the first updating operation being performed once.