A rupture control device may include an address control circuit configured to generate a rupture address in response to a first rupture command signal, a rupture mask signal and an external address, wherein the rupture address is generated according to whether the rupture mask signal is activated, and wherein an address and fuse data are compared, and a rupture mask signal indicating whether a fuse is ruptured is determined. Further, a fuse array configured to perform a rupture operation in response to the rupture address when a rupture enable signal is activated, and output the fuse data in response to a read enable signal.

A memory device including a memory cell array, a redundant fuse circuit and a memory controller is provided. The memory cell array includes multiple regular memory blocks and multiple redundant memory blocks. The redundant fuse circuit includes multiple fuse groups recording multiple repair information. Each repair information is associated with a corresponding one of the redundant memory blocks and includes a repair address, a first enable bit, and a second enable bit. The memory controller includes multiple determining circuits. Each of the multiple determining circuits generates a hit signal according to an operation address, the repair address, the first enable bit, and the second enable bit. When a target memory block is bad, and the determining circuit of the memory controller generates the hit signal, the memory controller disables the redundant memory block that is bad according to the hit signal.

Provided are a fuse blowing method and apparatus for a memory, a storage medium, and an electronic device. The method includes: controlling a memory to enter a test mode, and reducing an internal clock frequency of the memory (S210); starting a fuse blowing load mode, and controlling the memory to enter a fuse blowing mode (S220); enabling internal precharge of the memory, and writing a location of a fuse to be blown into a fuse blowing location register (S230); starting a fuse blowing process of the memory, and disabling the internal precharge after preset time (S240); and controlling the memory to exit the fuse blowing mode and the test mode successively (S250).

A memory device includes a fail test circuit configured to generate a fail flag indicating whether a failure was detected in a column line, on the basis of internal data outputted from the column line selected according to a column address, when performing a test, and control the fail flag to indicate that the failure was detected in the column line, on the basis of a fail control signal. The memory device also includes a repair information generation circuit configured to generate, from the column address, a repair column address for repairing the column line, on the basis of the fail flag.

A semiconductor memory device may include a cell array comprising a plurality of memory cells, each memory cell connected to a word line and a bit line, the cell array divided into a plurality of blocks, each block including a plurality of word lines, the plurality of blocks including at least a first defective block; a nonvolatile storage circuit configured to store address information of the first defective block, and to output the address information to an external device; and a fuse circuit configured to cut off an activation of word lines of the first defective block.

Methods, systems, and devices for modifying subsets of memory bank operating parameters are described. First global trimming information may be configured to adjust a first subset of operating parameters for a set of memory banks within a memory system. Second global trimming information may be configured to adjust a second subset of operating parameters for the set of memory banks. Local trimming information may be used to adjust one of the subsets of the operating parameters for a subset of the memory banks. To adjust one of the subsets of the operating parameters, the local trimming information may be combined with one of the first or second global trimming information to yield additional local trimming information that is used to adjust a corresponding subset of the operating parameters at the subset of the memory banks.

Apparatuses for memory repair for a memory device are described. An example apparatus includes: a non-volatile storage element that stores information; a storage latch circuit coupled to the non-volatile storage element and stores latch information; and a control circuit that, in a first repair mode, receives first repair address information, provides the first repair address information to the non-volatile storage element, and further transmits the first repair address information from the non-volatile storage element to the storage latch circuit. The control circuit, in a second repair mode, receives second repair address information and provides the second repair address information to the storage latch circuit and disables storing the second address information into the non-volatile storage element.

A fuse controller comprises: a fuse bay, a bus, an engine, and an interface. The fuse bay stores repair and setting information for a plurality of fuse domains in a linked-list data structure. The engine manages the linked-list data structure. The engine also is coupled to the fuse domains via the bus. The interface is coupled to the engine and receives commands and data for operating the engine.

A Fail Bit (FB) repair method and device can be applied to repairing an FB in a chip. The method includes: a bank to be repaired including multiple target repair banks in a chip to be repaired is determined; first repair processing is performed on a first FB in each target repair bank by using a redundant circuit; a second FB position determination step is executed to determine a bit position of a second FB, and second repair processing is performed on the second FB; unrepaired FBs in each target repair bank is determined, and the second FB position determination step is recursively executed to obtain a test repair position of each unrepaired FB to perform third repair processing on the unrepaired FB according to the test repair position.

A semiconductor device structure is provided. The semiconductor device structure includes a first gate structure, a second gate structure, and a first active region. The first gate structure extends along a first direction and is electrically connected to a first transistor. The second gate structure extends along the first direction and is electrically connected to a second transistor. The first active region extends along a second direction different from the first direction and across the first gate structure and the second gate structure. The first gate structure and the first active region collaboratively form a first fuse element. The second gate structure and the first active region collaboratively form a second fuse element.