A memory system includes a plurality of memories, each including a plurality of data input terminals; and a memory controller configured to continuously transfer a first codeword and a second codeword to the data input terminals of the memories during a write operation.

Disclosed herein is an apparatus that includes a fuse array circuit including a plurality of fuse sets each assigned to a corresponding one of a plurality of fuse addresses and configured to operatively store a fuse data, and a first circuit configured to generate and sequentially update a fuse address to sequentially read the fuse data from the plurality of fuse sets. The first circuit is configured to change a frequency of updating the fuse address based on a first signal.

The present disclosure provides a method for determining status of a fuse element of a memory device. The method includes providing the memory device including a first terminal and a second terminal and applying a first power signal on the first terminal of the semiconductor device. The memory device includes a configurable reference resistor unit electrically coupled to the fuse element. The method also includes obtaining an evaluation signal at the second terminal of the memory device and identifying the evaluation signal to determine whether the memory device is redundant. The configurable reference resistor unit includes a first resistor, a first transistor connected in parallel with the first resistor, and a first configurable unit connected to a gate of the first transistor. The first configurable unit is configured to generate a first configurable signal to turn on the first transistor.

Disclosed herein is an apparatus that includes first register circuits configured to store a first address, and a comparing circuit configured to compare the first address with a second address. The comparing circuit includes first and second circuit sections. In a first operation mode, the comparing circuit is configured to activate a match signal when the first circuit section detects that the first bit group of the first address matches with the third bit group of the second address and the second circuit section detects that the second bit group of the first address matches with the fourth bit group of the second address. In a second operation mode, the comparing circuit is configured to activate the match signal when the first circuit section detects that the first bit group matches with the third bit group regardless of the second and fourth bit groups.

An apparatus includes a potential failure information generation circuit configured to generate potential failure inforrnation by detecting, based on first failure information on a first faded signal line and second failure information on a second faded signal line, whether the first failed signal line and the second faded signal line are adjacent to each other; and a flag generation circuit configured to generate a flag by comparing the potential failure information with redundancy repair information.

A semiconductor apparatus may include a repair circuit configured to activate a redundant line of a cell array region by comparing repair information and address information. The semiconductor apparatus may include a main decoder configured to perform a normal access to the cell array region by decoding the address information. The address information may include both column information and row information.

The present disclosure provides a chip including an even area including an even through via through which an even address is received and an even redundancy through via through which an even redundancy address is received, and an odd area including an odd through via through which an odd address is received and an odd redundancy through via through which an odd redundancy address is received. In the present disclosure, the even area may include an even address selection circuit configured to, based on a chip information signal, generate a selection even address and a selection even redundancy address from the even address, the even redundancy address, the odd address, and the odd redundancy address, and an even internal address generation circuit configured to, based on an even repair signal, generate an internal even address from the selection even address and the selection even redundancy address.

A semiconductor apparatus may include a repair circuit configured to activate a redundant line of a cell array region by comparing repair information and address information. The semiconductor apparatus may include a main decoder configured to perform a normal access to the cell array region by decoding the address information. The address information may include both column information and row information.

A computer platform is disclosed. The computer platform comprises a non-volatile memory to store fuse override data; and a system on chip (SOC), coupled to the non-volatile memory, including a fuse memory to store fuse data and security micro-controller to receive the fuse override data and perform a fuse override to overwrite the fuse data stored in the fuse memory with the fuse override data.

An electronic device includes memory banks and repair circuitry configured to remap data from the memory banks to repair memory elements of the memory banks when a failure occurs. The repair circuitry includes a logic gate configured to receive an output from a memory bank of the memory banks, receive a failure signal indicating whether a corresponding memory element has failed, and transmit the output with a value of the output is based at least in part on the failure signal. The repair circuitry also includes error correction circuitry configured to receive the output via the logic gate and a multiplexer configured to receive the output from the memory bank, receive a repair value, and selectively output the output or the repair value from the repair circuitry as an output of the repair circuitry.