A method of repairing a memory device may include collecting fail information on fail cells in a multi-block memory, classifying the fail cells into first and second types, and repairing the fail cells in the multi-block memory using one or more of a global spare memory, a local spare memory, and a common spare memory, based on the fail information.

Provided is a memory device that has a structure suitable for still higher integration while securing production easiness, and includes n memory cell units stacked, on a substrate, in order as first to n-th memory cell units in a first direction. The n memory cell units each include: one or more first electrodes; a plurality of second electrodes each provided to intersect the first electrode; a plurality of memory cells provided at respective intersections of the first electrode and the second electrodes and each coupled to both the first and second electrodes; and one or more lead lines coupled to the first electrode to form one or more coupling parts, which, in (m+1)-th memory cell unit, are located at a position where the coupling parts and m-th memory cell region surrounded by the memory cells in m-th memory cell unit overlap each other in the first direction.

A main memory includes a first plurality of input/outputs (I/Os) configured to output data stored in the main memory in response to a read access request. A first portion of the first plurality of IOs provides user read data in response to the read access request and a second portion of the first plurality of IOs provides candidate replacement IOs. Repair circuitry is configured to selectively replace one or more IOs of the first portion of IOs using one or more of the candidate replacement IOs of the second portion of IOs to provide repaired read data in response to the read access request in accordance with repair mapping information corresponding to an access address of the read access request. A static random access memory (SRAM) stores repair mapping information, and a repair cache stores cached repair mapping information from the SRAM for address locations of the main memory.

Provided is a memory device that has a structure suitable for still higher integration while securing production easiness, and includes n memory cell units stacked, on a substrate, in order as first to n-th memory cell units in a first direction. The n memory cell units each include: one or more first electrodes; a plurality of second electrodes each provided to intersect the first electrode; a plurality of memory cells provided at respective intersections of the first electrode and the second electrodes and each coupled to both the first and second electrodes; and one or more lead lines coupled to the first electrode to form one or more coupling parts, which, in (m+1)-th memory cell unit, are located at a position where the coupling parts and m-th memory cell region surrounded by the memory cells in m-th memory cell unit overlap each other in the first direction.

A method of repairing a memory device may include collecting fail information on fail cells in a multi-block memory, classifying the fail cells into first and second types, and repairing the fail cells in the multi-block memory using one or more of a global spare memory, a local spare memory, and a common spare memory, based on the fail information.

Provided is a memory device that has a structure suitable for still higher integration while securing production easiness, and includes n memory cell units stacked, on a substrate, in order as first to n-th memory cell units in a first direction. The n memory cell units each include: one or more first electrodes; a plurality of second electrodes each provided to intersect the first electrode; a plurality of memory cells provided at respective intersections of the first electrode and the second electrodes and each coupled to both the first and second electrodes; and one or more lead lines coupled to the first electrode to form one or more coupling parts, which, in (m+1)-th memory cell unit, are located at a position where the coupling parts and m-th memory cell region surrounded by the memory cells in m-th memory cell unit overlap each other in the first direction.

A memory includes a plurality of columns and a redundant column. The memory includes a plurality of multiplexers corresponding to the plurality of columns. Depending upon the location of a defect, the multiplexers are configured to select for their corresponding column or an immediately-subsequent column to their corresponding column.

A memory includes a plurality of columns and a redundant column. The memory includes a plurality of multiplexers corresponding to the plurality of columns. Depending upon the location of a defect, the multiplexers are configured to select for their corresponding column or an immediately-subsequent column to their corresponding column.

A semiconductor device includes a fuse block configured to store repair information corresponding to a fail address, and output fuse data in a boot-up operation; a dummy mat formed in a predetermined region of a cell array, and configured to store the fuse data in the boot-up operation; and a repair latch block configured to store the fuse data in the boot-up operation, wherein the fuse data stored in the dummy mat are updated to and stored in the repair latch block in a refresh operation.

A semiconductor device includes a fuse block configured to store repair information corresponding to a fail address, and output fuse data in a boot-up operation; a dummy mat formed in a predetermined region of a cell array, and configured to store the fuse data in the boot-up operation; and a repair latch block configured to store the fuse data in the boot-up operation, wherein the fuse data stored in the dummy mat are updated to and stored in the repair latch block in a refresh operation.