A non-volatile memory system comprises a memory structure and a control circuit connected to the memory structure. The memory structure includes one or more planes of non-volatile memory cells. Each plane is divided into a plurality of partial planes. The control circuit is configured to write to and read from the memory cells by writing a partial page into a particular partial plane and reading the partial page from the particular partial plane using a set of parameters optimized for the particular partial plane.

A dynamic redundancy memory includes a redundancy control module and an ECC module. The ECC detects bit errors, stores the addresses of the error bits, counts the bit errors. If the number of errors exceeds a threshold, the ECC identifies the address as a suspect bit and sends a suspect bit signal to the redundancy control module, which determines whether the suspect bit address is already stored in a redundancy element. If already stored, the element is marked bad, the address of the suspect bit is replaced with a new redundant address and the suspect bit address is stored in a good unused element. The ECC determines whether the error occurrences at the address exceeds a bit error rate threshold. If the error rate threshold is exceeded, the ECC identifies the address as suspect bit and sends the suspect bit signal to the redundancy control module.

A non-volatile memory system comprises a memory structure and a control circuit connected to the memory structure. The memory structure includes one or more planes of non-volatile memory cells. Each plane is divided into a plurality of partial planes. The control circuit is configured to write to and read from the memory cells by writing a partial page into a particular partial plane and reading the partial page from the particular partial plane using a set of parameters optimized for the particular partial plane.

A non-volatile memory system comprises a memory structure and a control circuit connected to the memory structure. The memory structure includes one or more planes of non-volatile memory cells. Each plane is divided into a plurality of partial planes. The control circuit is configured to write to and read from the memory cells by writing a partial page into a particular partial plane and reading the partial page from the particular partial plane using a set of parameters optimized for the particular partial plane.

A dynamic redundancy memory includes a redundancy control module and an ECC module. The ECC detects bit errors, stores the addresses of the error bits, counts the bit errors. If the number of errors exceeds a threshold, the ECC identifies the address as a suspect bit and sends a suspect bit signal to the redundancy control module, which determines whether the suspect bit address is already stored in a redundancy element. If already stored, the element is marked bad, the address of the suspect bit is replaced with a new redundant address and the suspect bit address is stored in a good unused element. The ECC determines whether the error occurrences at the address exceeds a bit error rate threshold. If the error rate threshold is exceeded, the ECC identifies the address as suspect bit and sends the suspect bit signal to the redundancy control module.

The present embodiments provide a stacked memory apparatus and a repairing method thereof which store information about a spare resource in a pre-bond process, check a spare resource available in a post-bond process, correct an error through an error correction code, and variably use the same number of spare resources to additionally ensure a number of spare resources in the post-bond process, thereby improving a yield.

An embodiment of an electronic memory apparatus may include storage media, and logic communicatively coupled to the storage media, the logic to determine if a mode is set to one of a first mode or a second mode, perform a soft post package repair in the first mode, and undo the soft post package repair in the second mode. Other embodiments are disclosed and claimed.

A semiconductor apparatus includes a fuse array, a word line decoder, a bit line decoder, a bank information comparison circuit, and a rupture circuit. The word line decoder is configured to select a word line of the fuse array based on a bank select address signal. The bit line decoder is configured to select a bit line of the fuse array based on a fail row address signal. The bank information comparison circuit and the rupture circuit are configured to rupture a fuse coupled to the word line and the bit line when a fail bank address signal and the bank select address signal correspond to each other.

Numerous embodiments are disclosed for accessing redundant non-volatile memory cells in place of one or more rows or columns containing one or more faulty non-volatile memory cells during a program, erase, read, or neural read operation in an analog neural memory system used in a deep learning artificial neural network.

A memory-testing circuit configured to perform a test of reference bits in a memory. In a read operation, outputs of data bit columns are compared with one or more reference bit columns. The memory-testing circuit comprises: a test controller and association adjustment circuitry configurable by the test controller to associate another one or more reference bit columns or one or more data bit columns with the data bit columns in the read operation. The test controller can determine whether the original one or more reference bit columns have a defect based on results from the two different association.