An embodiment of a semiconductor apparatus may include technology to receive a request to modify a configuration of a persistent storage media, and repurpose a region of the persistent storage media from a first number of bits per cell to a second number of bits per cell in response to the request. Other embodiments are disclosed and claimed.

Exemplary methods, apparatuses, and systems include determining that data in a group of memory cells of a first memory device is to be moved to a spare group of memory cells. The group of memory cells spans a first dimension and a second dimension that is orthogonal to the first dimension and the spare group of memory cells also spans the first dimension and the second dimension. The data is read from the group of memory cells along the first dimension of the group of memory cells. The data is written to the spare group of memory cells along the second dimension of the spare group of memory cells.

A memory device includes a memory array with memory blocks each having a plurality of memory cells, and one or more current monitors configured to measure current during post-deployment operation of the memory device; and a controller configured to identify a bad block within the memory blocks based on the measured current, and disable the bad block for preventing access thereof during subsequent operations of the memory device.

A memory controller includes a memory interface and a processor. The processor is coupled to the memory interface and controls access operation of a memory device via the memory interface. The processor maintains a predetermined table according to write operation of a first memory block of the memory device and performs data protection in response to the write operation. When performing the data protection, the processor determines whether memory space damage has occurred in the first memory block. When it is determined that memory space damage has occurred in the first memory block, the processor traces back one or more data sources of data written in the first memory block according to the predetermined table to obtain address information of one or more source memory blocks and performs a data recovery operation according to the address information of the one or more source memory blocks.

A memory device includes a plurality of planes, a row driver and a controller. A method of programming the memory device includes in a program operation, the row driver applying a program pulse to a plurality of memory cells of a first plane of the plurality of planes; after the row driver applies the program pulse to the plurality of memory cells, the controller verifying if the plurality of memory cells have reached a predetermined program state; and if a preset number of the plurality of memory cells have failed to reach the predetermined program state after the plurality of memory cells have been verified for a predetermined number of times, the controller disabling the first plane.

Apparatuses and methods for repairing memory devices including a plurality of memory die and an interface are disclosed. An example apparatus includes a first stack that includes a plurality of first dies stacked with one another, the first dies include a plurality of first channels, at least one of which is designated as a first defective channel, and further includes a second stack stacked with the first stack and including a plurality of second dies stacked with one another, the second dies including a plurality of second channels, at least one of which is designated as a second defective channel. A control circuit is configured, responsive to a command for accessing the first defective channel, to access one of the plurality of second channels in place of accessing the first defective channel, wherein the one of the plurality of second channels corresponds to the first defective channel and is not designated as the second defective channel.

A memory device includes a plurality of planes, a row driver and a controller. A method of programming the memory device includes in a program operation, the row driver applying a program pulse to a plurality of memory cells of a first plane of the plurality of planes; after the row driver applies the program pulse to the plurality of memory cells, the controller verifying if the plurality of memory cells have reached a predetermined program state; and if a preset number of the plurality of memory cells have failed to reach the predetermined program state after the plurality of memory cells have been verified for a predetermined number of times, the controller disabling the first plane.

A volatile memory device is configured to self-document by identifying its own bad or at-risk excludable memory locations in a nonvolatile identification embedded in itself, without using additional board real estate. The identification of bad or at-risk memory is readable by firmware outside the device. The device includes volatile memory cells that have respective failure susceptibility values, some of which indicate bad or at-risk memory cells. The memory device also includes read logic and write logic, and may include refresh logic. The identification may be embedded in the device by blowing fuses in an adaptation of self-repair activity, or by writing identification data into a serial presence detect logic, for example. The configured memory device may efficiently, persistently, and reliably provide detailed memory test results regarding itself, thereby allowing customers to accept and safely use memory that would otherwise have been discarded to prevent software crashes.

A volatile memory device is configured to self-document by identifying its own bad or at-risk excludable memory locations in a nonvolatile identification embedded in itself, without using additional board real estate. The identification of bad or at-risk memory is readable by firmware outside the device. The device includes volatile memory cells that have respective failure susceptibility values, some of which indicate bad or at-risk memory cells. The memory device also includes read logic and write logic, and may include refresh logic. The identification may be embedded in the device by blowing fuses in an adaptation of self-repair activity, or by writing identification data into a serial presence detect logic, for example. The configured memory device may efficiently, persistently, and reliably provide detailed memory test results regarding itself, thereby allowing customers to accept and safely use memory that would otherwise have been discarded to prevent software crashes.

Memory devices and systems with post-packaging master die selection, and associated methods, are disclosed herein. In one embodiment, a memory device includes a plurality of memory dies. Each memory die of the plurality includes a command/address decoder. The command/address decoders are configured to receive command and address signals from external contacts of the memory device. The command/address decoders are also configured, when enabled, to decode the command and address signals and transmit the decoded command and address signals to every other memory die of the plurality. Each memory die further includes circuitry configured to enable, or disable, or both individual command/address decoders of the plurality of memory dies. In some embodiments, the circuitry can enable a command/address decoder of a memory die of the plurality after the plurality of memory dies are packaged into a memory device.