A memory controller including: a fault determination circuit to receive first parity, second parity, and data read out from a first row of a memory device, and determine, based on a result of a first error detection operation using the first parity and a result of a second error detection operation using the second parity, whether the first row is faulty; a parity storage circuit to store a repair parity for repairing a fault of a row of a plurality of rows of the memory device, wherein the plurality of rows constitutes a repair unit, and wherein the repair unit includes the first row and one or more second rows; and a recovery circuit to repair a fault of the first row by using data of at least one of the second rows and the repair parity, when the first row is determined to be a faulty row.

A data storage device may include: a storage configured as a group of a plurality of memory blocks; and a controller configured to: control data input/output of the storage according to a request transferred from a host device; configure one or more first block groups by grouping a preset number of memory blocks which are selected at the same time among the memory blocks during an operation of the storage; configure one or more second block groups by replacing a bad memory block of the respective first block groups with a spare memory block; manage as a special block group a second block group where the spare memory block having replaced the bad memory block is not present in the same plane of the bad memory block, among the second block groups; and write data having a preset property to the special block group.

Disclosed in some examples are NAND devices, firmware, systems, methods, and devices that apply smart algorithms to process ECC errors by taking advantage of excess overprovisioning. In some examples, when the amount of overprovisioned blocks are above a predetermined threshold, a first ECC block error handling mode may be implemented and when the overprovisioned blocks are equal or less than the predetermined threshold, a second mode of ECC block error handling may be utilized.

A memory system includes: a memory device; a run-time bad block detector suitable for storing information of super memory blocks, each including a run-time bad block, in a bad list; a bit-map manager suitable for generating a bit-map representing integrity information of memory blocks in each of the super memory blocks; a short super block manager suitable for designating, among the super memory blocks, a super memory block having a number of run-time bad blocks less than or equal to a threshold as a short super memory block based on the bad list and the bit-map, whenever a logical unit configuration command is received from a host; and a processor suitable for controlling the memory device to simultaneously access normal blocks among the memory blocks forming the designated short super memory block and to perform a normal operation, based on the bit-map.

Methods, systems, and devices for speculative memory section selection are described. Defective memory components in one memory section may be repaired using repair components in another memory section. Speculative selection of memory sections may be enabled, whereby access lines in multiple memory sections may be selected when a memory command indicating an address in one memory section is received. While the access lines in the multiple memory sections are selected, a determination of whether repair components in another memory section are to be accessed is performed. Based on the determination, the access line in one of the memory sections may be maintained and the access lines in the other memory sections may be deselected.

Methods, systems, and devices for speculative memory section selection are described. Defective memory components in one memory section may be repaired using repair components in another memory section. Speculative selection of memory sections may be enabled, whereby access lines in multiple memory sections may be selected when a memory command indicating an address in one memory section is received. While the access lines in the multiple memory sections are selected, a determination of whether repair components in another memory section are to be accessed is performed. Based on the determination, the access line in one of the memory sections may be maintained and the access lines in the other memory sections may be deselected.

Disclosed are a memory device and an operating method thereof, and the memory device includes a plurality of first data lines, a plurality of second data lines, a common redundant memory region coupled to at least one repair line of the second data lines, a plurality of normal memory regions coupled to the first data lines in common, and coupled in common to the remaining the second data lines excluding the repair line, and a repair circuit coupled to the first and second data lines, and suitable for replacing at least one defective memory cell in the normal memory regions with at least one redundant memory cell in the common redundant memory region by shifting some or all of the first data lines to some or all of the second data lines, based on a row address, a column address and a region address.

A memory system includes a memory device including a plurality of blocks, and a controller suitable for managing the plurality of blocks by grouping the plurality of blocks into a plurality of super blocks in accordance with a predetermined condition, managing normal blocks which are not grouped into the super blocks in a replacement block pool, setting each of the plurality of super blocks that includes at least one bad block to a bad super block, and then changing each bad super block in which the at least one bad block is replaced with a normal block of the replacement block pool using replacement information to a recovery super block, wherein the replacement information includes in a bitmap indicative of whether or not an interleaving operation of each of the recovery super blocks is possible.

Some examples described herein relate to redundancy in a multi-chip stacked device. An example described herein is a multi-chip device. The multi-chip device includes a chip stack including vertically stacked chips. Neighboring pairs of the chips are directly connected together. Each of two or more of the chips includes a processing integrated circuit. The chip stack is configurable to operate a subset of functionality of the processing integrated circuits of the two or more of the chips when any portion of the processing integrated circuits is defective.

A semiconductor memory apparatus includes a plurality of memory dies and a logic die, which are stacked to each other. The logic die includes a memory interface for a memory apparatus to be coupled to the semiconductor memory apparatus, and a switch coupled to a plurality of channels included in a control device which controls the semiconductor memory apparatus. The switch includes a first switch element which couples one of the plurality of channels to the memory interface or one of the plurality of memory dies, and a second switch element which couples another one of the plurality of channels to another one of the plurality of memory dies. Even if some memory dies are defective, the semiconductor memory apparatus is capable to operate.