A memory device and a multiple cells error correction in a memory cell is provided. The memory device includes a plurality of memory cells and a memory control circuit. Each of the memory cells includes a first type physical cell and a second type physical cell. The memory control circuit is coupled to each of the memory cells. The memory control circuit writes a writing data into the first type physical cell and verifies the data stored in the first type physical cell is same as the writing data or not. The writing data is set and processed by performing a write operation. The memory control circuit writes the writing data into the second type physical cell when the data stored in the first type physical cell is not same as the writing data.

A semiconductor device includes an error check and scrub (ECS) command generation circuit and a period signal generation circuit. The ECS command generation circuit generates an ECS command based on a refresh command. The period signal generation circuit generates a sampling period signal, during a sampling period, based on the ECS command and generates an operation period signal, during an operation period, based on the ECS command. A latch error flag is generated to include information on whether errors exist in codewords during the sampling period, and an ECS operation is performed based on the latch error flag, during the operation period, for memory cells that store an erroneous codeword among the codewords.

A semiconductor device includes an error check and scrub (ECS) command generation circuit and an ECS control circuit. The ECS command generation circuit is configured to generate an ECS command by controlling a speed of a first counting operation that is performed based on a refresh command or a bank refresh command, according to a temperature and a refresh mode of the semiconductor device, or is configured to generate the ECS command by performing a second counting operation based on a periodic signal. The ECS control circuit is configured to sequentially generate an ECS active command, an ECS read command, an ECS write command, an ECS pre-charge command, and an end signal based on the ECS command. The refresh mode includes a fine granularity refresh (FGR) mode, and the temperature includes a high temperature that is a temperature above a certain temperature.

Methods, systems, and apparatuses for memory (e.g., DRAM) having an error check and scrub (ECS) procedure in conjunction with refresh operations are described. While a refresh operation reads the code words of a memory row, ECS procedures may be performed on some of the sensed code words. When the write portion of the refresh begins, a code word discovered to have errors may be corrected before it is written back to the memory row. The ECS procedure can be incremental across refresh operations, beginning, for example, each ECS at the code word where the pervious ECS for that row left off. The ECS procedure can include an out-of-order (OOO) procedure where ECS is performed more often for certain identified code words.

A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, an input/output (I/O) gating circuit connected between the memory cell array and the ECC engine, an error information register and a control logic circuit. The memory cell array includes a plurality of memory cell rows. The control logic circuit controls the ECC engine, the I/O gating circuit and the error information register based on a command and address. The I/O gating circuit provides the ECC engine with codewords which are read from the memory cell array through refresh operations on the plurality of memory cell rows. The ECC engine performs an ECC decoding on main data of the codewords based on parity bits of the codewords and provides error generation signals to the control logic circuit in response to detecting correctable errors with respect to a corresponding address resulting from performing the ECC decoding.

The provided is a method of controlling a dynamic random-access memory (DRAM) device comprising: storing a plurality of pieces of data consisting of a plurality of bits in a memory in a transposed manner; setting at least one refresh period for each of a plurality of rows constituting the memory; and performing a refresh operation of the memory on the basis of the set refresh period.

A memory system includes a memory device having a plurality of volatile memory modules therein, and a memory controller, which is electrically coupled to the plurality of volatile memory modules. The memory controller is configured to correct an error in a first of the plurality of volatile memory modules in response to generation of an alert signal by the first of the plurality of volatile memory modules, concurrently with an operation to refresh at least a portion of a second of the plurality of volatile memory modules upon the generation of the alert signal.

A deferred error correction code (ECC) scheme for memory devices is disclosed. In one embodiment, a method is disclosed comprising starting a deferred period of operation of a memory system in response to detecting the satisfaction of a condition; receiving an operation during the deferred period, the operation comprising a read or write operation access one or more memory banks of the memory system; deferring ECC operations for the operation; executing the operation; detecting an end of the deferred period of operation; and executing the ECC operations after the end of the deferred period.

A semiconductor memory device includes an ECC circuit; an error information register; a scrubbing control circuit to count refresh row addresses and output a scrubbing address for a scrubbing operation to be performed on at least one sub-page in a first memory cell row each time N refresh row addresses are counted; and a control logic circuit configured to: control the ECC circuit to sequentially read data corresponding to a first codeword, perform error detection on the first codeword, and provide error information based on the error detection, the error information indicating an error occurrence count in the first codeword; and record the error information in the error information register and selectively determine, based on the error information, whether to write back a corrected first codeword in a memory location in which the data corresponding to the first codeword is stored.

Embodiments of the present invention include a memory module that includes a plurality of memory devices and a memory buffer device. The memory devices are characterized as one of a high or low random bit error rate (RBER) memory device. The memory buffer device includes a read data interface to receive data read from a memory address on one of the memory devices, and common error correction logic to detect and correct error conditions in data read from both high RBER and low RBER memory devices. The memory buffer device also includes refresh rate logic configured to adjust a refresh rate based on the detected error conditions.