An integrated circuit (IC) memory device includes an array of storage cells configured into multiple banks. Interface circuitry receives refresh commands from a host memory controller to refresh the multiple banks for a first refresh mode. On-die refresh control circuitry selectively generates local refresh commands to refresh the multiple banks in cooperation with the host memory controller during a designated hidden refresh interval in a second refresh mode. Mode register circuitry stores a value indicating whether the on-die refresh control circuitry is enabled for use during the second refresh mode. The interface circuitry includes backchannel control circuitry to transmit a corrective action control signal during operation in the second refresh mode.

A memory device includes memory banks that each has multiple rows with row addresses. The memory device also includes a counter that stores and increments a first row address of a first row of a first set of memory banks to a second row address of a second row of the first set of memory banks in response to a first refresh operation when the memory device is operating in a first mode. The memory device further includes circuitry that blocks incrementing the second row address to a third row address of a third row of the first set of memory banks when the memory device transitions from the first mode to a second mode and the first refresh operation is not paired with a second refresh operation that is performed when the memory device is operating in the first mode.

A memory device includes memory banks that each has multiple rows with row addresses. The memory device also includes a counter that stores and increments a first row address of a first row of a first set of memory banks to a second row address of a second row of the first set of memory banks in response to a first refresh operation when the memory device is operating in a first mode. The memory device further includes circuitry that blocks incrementing the second row address to a third row address of a third row of the first set of memory banks when the memory device transitions from the first mode to a second mode and the first refresh operation is not paired with a second refresh operation that is performed when the memory device is operating in the first mode.

A memory device includes memory banks that each has multiple rows with row addresses. The memory device also includes a counter that stores and increments a first row address of a first row of a first set of memory banks to a second row address of a second row of the first set of memory banks in response to a first refresh operation when the memory device is operating in a first mode. The memory device further includes circuitry that blocks incrementing the second row address to a third row address of a third row of the first set of memory banks when the memory device transitions from the first mode to a second mode and the first refresh operation is not paired with a second refresh operation that is performed when the memory device is operating in the first mode.

A refreshing method is described. The method includes recognizing a set of blocks of a non-volatile memory for refreshing and then refreshing a subset of the data within the blocks, where, invalid data within the blocks is not recognized for refreshing and a group of blocks whose oldest data has not aged for a pre-set time period is not recognized for refreshing.

A method of ECC encoding a DRAM and a DRAM thereof. The method comprises determining whether to encode the data according to the value of a flag bit while the DRAM is being refreshed. The ECC encoding module encodes data only if of the flag bit setting and detecting module generates an enable signal. As a result, the length of the valid data for ECC encoding can be guaranteed to comply with the requirements of ECC encoding.

A memory device includes memory banks that each has multiple rows with row addresses. The memory device also includes a counter that stores and increments a first row address of a first row of a first set of memory banks to a second row address of a second row of the first set of memory banks in response to a first refresh operation when the memory device is operating in a first mode. The memory device further includes circuitry that blocks incrementing the second row address to a third row address of a third row of the first set of memory banks when the memory device transitions from the first mode to a second mode and the first refresh operation is not paired with a second refresh operation that is performed when the memory device is operating in the first mode.

An integrated circuit (IC) memory device includes an array of storage cells configured into multiple banks. Interface circuitry receives refresh commands from a host memory controller to refresh the multiple banks for a first refresh mode. On-die refresh control circuitry selectively generates local refresh commands to refresh the multiple banks in cooperation with the host memory controller during a designated hidden refresh interval in a second refresh mode. Mode register circuitry stores a value indicating whether the on-die refresh control circuitry is enabled for use during the second refresh mode. The interface circuitry includes backchannel control circuitry to transmit a corrective action control signal during operation in the second refresh mode.

A memory device includes memory banks that each has multiple rows with row addresses. The memory device also includes a counter that stores and increments a first row address of a first row of a first set of memory banks to a second row address of a second row of the first set of memory banks in response to a first refresh operation when the memory device is operating in a first mode. The memory device further includes circuitry that blocks incrementing the second row address to a third row address of a third row of the first set of memory banks when the memory device transitions from the first mode to a second mode and the first refresh operation is not paired with a second refresh operation that is performed when the memory device is operating in the first mode.

A memory circuit, comprises a first set of memory cells configured to operate in a direct access mode or in a refresh mode and a second set of memory cells configured to operate in the direct access mode and in the refresh mode. The memory circuit further comprises a controller configured to receive a write request and to execute the write request for a set of memory cells being in direct access mode; and to buffer the write request for later execution for a set of memory cells being in refresh mode.