Disclosed herein is an apparatus that includes a plurality of address registers each storing an address signal, a plurality of counter circuits each storing a count value corresponding to an associated one of the address registers, a first circuit cyclically selecting one of the address registers in response to a first signal, a second circuit selecting one of the address registers based on the count value of each of the counter circuits, and a third circuit activating a second signal when the first and second circuits select the same one of the address registers.

A semiconductor memory device includes a cell array including a plurality of word lines; a plurality of address storing circuits, each of the plurality of address storing circuits suitable for storing a sampling address as a latch address, a valid bit indicating whether the latch address is valid, and a valid-lock bit indicating whether the latch address is accessed more than a certain number of times, each of the plurality of address storing circuits further suitable for outputting the latch address as a target address according to the valid bit and valid-lock bit; and a row control circuit suitable for refreshing one or more word lines based on the target address in response to a refresh command.

Methods, apparatuses, and systems for staggering refresh operations to memory arrays in different dies of a three-dimensional stacked (3DS) memory device are described. A 3DS memory device may include one die or layer of that controls or regulates commands, including refresh commands, to other dies or layers of the memory device. For example, one die of the 3DS memory may delay a refresh command when issuing the multiple concurrent memory refreshes would cause some problematic performance condition, such as high peak current, within the memory device.

A semiconductor memory device includes a cell array including a plurality of word lines; a plurality of address storing circuits, each of the plurality of address storing circuits suitable for storing a sampling address as a latch address, a valid bit indicating whether the latch address is valid, and a valid-lock bit indicating whether the latch address is accessed more than a certain number of times, each of the plurality of address storing circuits further suitable for outputting the latch address as a target address according to the valid bit and valid-lock bit; and a row control circuit suitable for refreshing one or more word lines based on the target address in response to a refresh command.

Methods, systems, and devices for biasing a memory cell during a read operation are described. For example, a memory device may bias a memory cell to a first voltage (e.g., a read voltage) during an activation phase of a read operation. After biasing the memory cell to the first voltage, the memory device may bias the memory cell to a second voltage greater than the first voltage (e.g., a write voltage) during the activation phase of the read operation. After biasing the memory cell to the second voltage, the memory device may initiate a refresh phase of the read operation. Based on a value stored by the memory cell prior to biasing the memory cell to the first voltage, the memory device may initiate a precharge phase of the read operation.

An apparatus may include multiple address registers each storing an address signal and multiple counter circuits each storing a count value corresponding to an associated one of the address registers. The apparatus may include a first circuit cyclically selecting one of the address registers in response to a first signal, a second circuit selecting one of the address registers based on the count value of each of the counter circuits, and a third circuit activating a second signal when the first and second circuits select the same one of the address registers.

A system for refresh operations in semiconductor memories, and an apparatus and method therefore, are described. The system includes, for example, memory cells in memory banks that are refreshed during a self-refresh operation or an auto refresh operation. The self-refresh operation includes a different number of refresh activations than the auto refresh operation. The system further includes a row control circuit configured to refresh the memory cells in the memory banks based on refresh control signals received from a refresh control circuit, the refresh control signals provided by the refresh control circuit based on internal control signals received by the refresh control circuit from a command control circuit. The auto refresh operation includes a per bank refresh operation configured to refresh a corresponding memory bank or an all-bank refresh operation configured to refresh all memory banks.

A pseudo static random access memory including a plurality of memory chips and an information storing device is provided. The memory chips transmit a plurality of read/write data strobe signals to a memory controller by using a same bus. Regardless of whether a self refresh collision occurs in the memory chips, when the memory chips perform a read operation, read latency of the memory chips is set to be a fixed period that self refresh is allowed to be completed. The fixed period is greater than initial latency. The information storing device is configured to store information which defines the fixed period. The read/write data strobe signal indicates whether the self refresh collision occurs in the memory chips, and a level of the read/write data strobe signals is constant during the read latency. A method for operating a pseudo static random access memory is also provided.

Disclosed herein is an apparatus that includes a memory cell array including a plurality of memory cells, a first counter circuit configured to periodically update a count value during a first operation mode, a burst clock generator configured to successively generate a burst pulse predetermined times When the count value indicates a predetermined value, and a row address control circuit configured to perform a refresh operation on the memory cell array in response to the burst pulse.

Methods of operating a memory device are disclosed. A method may include determining an operating temperature of a memory bank of a memory device. The method may also include adjusting at least one refresh interval for the memory bank based on the operating temperature of the memory bank. Further, the method may include skipping at least one refresh of the memory bank based on at least one of the operation temperature of the memory bank and a number of active signals received at the memory bank. A memory device and an electronic system are also described.