The beginning of using Complementary Metal-Oxide-Semiconductor (CMOS) process technology to implement Static Random-Access Memory (SRAM) which transistor number is six. And then reducing transistor number for increasing integration density, but it will diminish the stability of memory, and also may enhance the complexity of access circuit, thus increasing the power consumption. For increasing the integration density of SRAM, and according to the electrical characteristics of reduced transistor number therefore designing the memory possess low power consumption and its corresponding circuits, and then implementing an access system. If electrical characteristic of the other various memories are similar to SRAM, such as Dynamic Random-Access Memory (DRAM), so they can also use the corresponding access circuit of SRAM.

In a control method, external data input to the pseudo static random access memory with a reference clock signal in a write operation are counted to generate a first count value. Data written to a dynamic memory array of the pseudo static random access memory with a built-in clock signal in the write operation are counted to generate a second count value. An initial cycle of the built-in clock signal is smaller than a cycle of the reference clock signal. The first count value is compared with the second count value. When the first count value is equal to the second count value, a write match signal is enabled. When the enabled write match signal is received, the write operation is converted from an asynchronous mode to a synchronous mode to adjust the cycle of the built-in clock signal to be equal to the cycle of the reference clock signal.

Described herein are two transistor (2T) memory cells that use TFTs as access and gain transistors. When one or both transistors of a 2T memory cell are implemented as TFTs, these transistors may be provided in different layers above a substrate, enabling a stacked architecture. An example 2T memory cell includes an access TFT provided in a first layer over a substrate, and a gain TFT provided in a second layer over the substrate, the first layer being between the substrate and the second layer (i.e., the gain TFT is stacked in a layer above the access TFT). Stacked TFT based 2T memory cells allow increasing density of memory cells in a memory array having a given footprint area, or, conversely, reducing the footprint area of the memory array with a given memory cell density.

A pseudo-static random access memory includes a control unit, which controls the refresh operations of the memory to be performed as many times as the number of refresh requests that are generated during a period after the first transaction ended and before a second transaction which is after the first transaction.

The beginning of using Complementary Metal-Oxide-Semiconductor (CMOS) process technology to implement Static Random-Access Memory (SRAM) which transistor number is six. And then reducing transistor number for increasing integration density, but it will diminish the stability of memory, and also may enhance the complexity of access circuit, thus increasing the power consumption. For increasing the integration density of SRAM, and according to the electrical characteristics of reduced transistor number therefore designing the memory possess low power consumption and its corresponding circuits, and then implementing an access system. If electrical characteristic of the other various memories are similar to SRAM, such as Dynamic Random-Access Memory (DRAM), so they can also use the corresponding access circuit of SRAM.

The beginning of using Complementary Metal-Oxide-Semiconductor (CMOS) process technology to implement Static Random-Access Memory (SRAM) which transistor number is six. And then reducing transistor number for increasing integration density, but it will diminish the stability of memory, and also may enhance the complexity of access circuit, thus increasing the power consumption. For increasing the integration density of SRAM, and according to the electrical characteristics of reduced transistor number therefore designing the memory possess low power consumption and its corresponding circuits, and then implementing an access system. If electrical characteristic of the other various memories are similar to SRAM, such as Dynamic Random-Access Memory (DRAM), so they can also use the corresponding access circuit of SRAM.

The beginning of using Complementary Metal-Oxide-Semiconductor (CMOS) process technology to implement Static Random-Access Memory (SRAM) which transistor number is six. And then reducing transistor number for increasing integration density, but it will diminish the stability of memory, and also may enhance the complexity of access circuit, thus increasing the power consumption. For increasing the integration density of SRAM, and according to the electrical characteristics of reduced transistor number therefore designing the memory possess low power consumption and its corresponding circuits, and then implementing an access system. If electrical characteristic of the other various memories are similar to SRAM, such as Dynamic Random-Access Memory (DRAM), so they can also use the corresponding access circuit of SRAM.

A pseudo static random access memory (SRAM) and a refresh method for a pseudo SRAM are provided. The refresh method includes: providing a basic clock signal; at a first time point, enabling a chip enable signal to perform a first write operation, and receiving write data during an enabled time period of the chip enable signal; at a delay time point after the first time point, enabling a sub-word line driving signal, and writing the write data to at least one selected sense amplifier during an enabled time period of the sub-word line driving signal; and receiving a refresh request signal, and determining whether the refresh request signal is enabled according to an end time point of the enabled time period of the chip enable signal to determine a timing of starting a refresh operation.

In a control method, external data input to the pseudo static random access memory with a reference clock signal in a write operation are counted to generate a first count value. Data written to a dynamic memory array of the pseudo static random access memory with a built-in clock signal in the write operation are counted to generate a second count value. An initial cycle of the built-in clock signal is smaller than a cycle of the reference clock signal. The first count value is compared with the second count value. When the first count value is equal to the second count value, a write match signal is enabled. When the enabled write match signal is received, the write operation is converted from an asynchronous mode to a synchronous mode to adjust the cycle of the built-in clock signal to be equal to the cycle of the reference clock signal.

A pseudo static random access memory (SRAM) and a refresh method for a pseudo SRAM are provided. The refresh method includes: providing a basic clock signal; at a first time point, enabling a chip enable signal to perform a first write operation, and receiving write data during an enabled time period of the chip enable signal; at a delay time point after the first time point, enabling a sub-word line driving signal, and writing the write data to at least one selected sense amplifier during an enabled time period of the sub-word line driving signal; and receiving a refresh request signal, and determining whether the refresh request signal is enabled according to an end time point of the enabled time period of the chip enable signal to determine a timing of starting a refresh operation.