The beginning of using Complementary Metal-Oxide-Semiconductor (CMOS) process technology to implement Static Random-Access Memory (SRAM) which transistor number is six. And then reducing transistor number for increasing integration density, but it will diminish the stability of memory, and also may enhance the complexity of access circuit, thus increasing the power consumption. For increasing the integration density of SRAM, and according to the electrical characteristics of reduced transistor number therefore designing the memory possess low power consumption and its corresponding circuits, and then implementing an access system. If electrical characteristic of the other various memories are similar to SRAM, such as Dynamic Random-Access Memory (DRAM), so they can also use the corresponding access circuit of SRAM.

Described herein are two transistor (2T) memory cells that use TFTs as access and gain transistors. When one or both transistors of a 2T memory cell are implemented as TFTs, these transistors may be provided in different layers above a substrate, enabling a stacked architecture. An example 2T memory cell includes an access TFT provided in a first layer over a substrate, and a gain TFT provided in a second layer over the substrate, the first layer being between the substrate and the second layer (i.e., the gain TFT is stacked in a layer above the access TFT). Stacked TFT based 2T memory cells allow increasing density of memory cells in a memory array having a given footprint area, or, conversely, reducing the footprint area of the memory array with a given memory cell density.

Techniques are provided for operating a memory package and more specifically to increasing bandwidth of a system having stacked memory. In an example, a system can include a storage device having a first type of volatile memory and a second type of volatile memory, and a host device coupled to the storage device. The host device can issue commands to the storage device to store and retrieve information of the system. The host device can include a memory map of the storage device and latency information associated with each command of the commands. The host can sort and schedule pending commands according to the latency information and can intermix commands for the first type of volatile memory and commands for the second type of volatile memory to maintain a high utilization or efficiency of a data interface between the host device and the storage device.

The present disclosure provides a memory device, which includes a first memory array, and a memory control circuit. The memory control circuit performs a first memory access operation in response to a first clock pulse of a control internal clock signal. The memory control circuit generates a first reset signal and asserts a first bit-line precharge signal in response to completion of the first memory access operation, and generates a second reset signal using the first reset signal and a second bit-line precharge signal obtained from the first bit-line precharge signal. The memory control circuit generates a second clock pulse of the control internal clock in response to the second reset signal, and performs a second memory access operation associated with the second memory access command at the second clock pulse.

A SRAM cell comprising two PMOS transistors and two NMOS transistors is fabricated with CMOS process technology. The PMOS transistors are coupled to a supply voltage rail, a first storage node and a second storage node. The NMOS transistors are responsive to a word line and coupled to the first and the second storage nodes and a bit line pair. When the two NMOS transistors are turned off, a floating voltage at the first storage node rises from a ground voltage and stabilizes at a steady-state voltage V.sub.stdf and a difference voltage (V.sub.DDV.sub.stdf) between the first and the second storage nodes is greater than a predefined voltage so that a data bit stored in the SRAM cell is read out correctly in a following data read period, where 0<V.sub.stdf<V.sub.DD.

A SRAM cell comprising two PMOS transistors and two NMOS transistors is fabricated with CMOS process technology. The PMOS transistors are coupled to a supply voltage rail, a first storage node and a second storage node. The NMOS transistors are responsive to a word line and coupled to the first and the second storage nodes and a bit line pair. When the two NMOS transistors are turned off, a floating voltage at the first storage node rises from a ground voltage and stabilizes at a steady-state voltage V.sub.stdf and a difference voltage (V.sub.DDV.sub.stdf) between the first and the second storage nodes is greater than a predefined voltage so that a data bit stored in the SRAM cell is read out correctly in a following data read period, where 0<V.sub.stdf<V.sub.DD.