The present embodiments provide a system that supports self-refreshing operations in a memory device. During operation, the system transitions the memory device from an auto-refresh state, wherein a memory controller controls refreshing operations for the memory device, to a self-refresh state, wherein the memory device controls the refreshing operations. While the memory device is in the self-refresh state, the system sends progress information for the refreshing operations from the memory device to the memory controller. Next, upon returning from the self-refresh state to the auto-refresh state, the system uses the progress information received from the memory device to control the sequencing of subsequent operations by the memory controller.

A pseudo static random access memory including a plurality of memory chips and an information storing device is provided. The memory chips transmit a plurality of read/write data strobe signals to a memory controller by using a same bus. Regardless of whether a self refresh collision occurs in the memory chips, when the memory chips perform a read operation, read latency of the memory chips is set to be a fixed period that self refresh is allowed to be completed. The fixed period is greater than initial latency. The information storing device is configured to store information which defines the fixed period. The read/write data strobe signal indicates whether the self refresh collision occurs in the memory chips, and a level of the read/write data strobe signals is constant during the read latency. A method for operating a pseudo static random access memory is also provided.

Methods for reducing boot time of a system-on-a-chip (SOC) by reducing double data rate (DDR) memory training and memory context restore. Dynamic random access memory (DRAM) controller and DDR physical interface (PHY) settings are stored into a non-volatile memory and the DRAM controller and DDR PHY are powered down. On system resume, a basic input/output system restores the DRAM controller and DDR PHY settings from non-volatile memory, and finalizes the DRAM controller and DDR PHY settings for operation with the SOC. Reducing the boot time of the SOC by reducing DDR training includes setting DRAMs into self-refresh mode, and programing a self-refresh state machine memory operation (MOP) array to exit self-refresh mode and update any DRAM device state for the target power management state. The DRAM device is reset, and the self-refresh state machine MOP array reinitializes the DRAM device state for the target power management state.

Disclosed are various embodiments related to stacked memory devices, such as DRAMs, SRAMs, EEPROMs, ReRAMs, and CAMs. For example, stack position identifiers (SPIDs) are assigned or otherwise determined, and are used by each memory device to make a number of adjustments. In one embodiment, a self-refresh rate of a DRAM is adjusted based on the SPID of that device. In another embodiment, a latency of a DRAM or SRAM is adjusted based on the SPID. In another embodiment, internal regulation signals are shared with other devices via TSVs. In another embodiment, adjustments to internally regulated signals are made based on the SPID of a particular device. In another embodiment, serially connected signals can be controlled based on a chip SPID (e.g., an even or odd stack position), and whether the signal is an upstream or a downstream type of signal.

Disclosed herein is an apparatus that includes a memory cell array including a plurality of memory cells, a first counter circuit configured to periodically update a count value during a first operation mode, a burst clock generator configured to successively generate a burst pulse predetermined times When the count value indicates a predetermined value, and a row address control circuit configured to perform a refresh operation on the memory cell array in response to the burst pulse.

An apparatus may include a semiconductor device that includes an internal clock circuit configured to receive an internal clock signal and to provide a local clock signal based on the internal clock signal. The internal clock circuit comprises a clock synchronizer configured to, in response to receipt of a command to exit a self-refresh mode, disable provision of the local clock signal by a number of cycles of the internal clock signal.

A signal calibration method that includes the steps outlined below is provided. A phase of an under-test signal generated by a memory controller is set to initiate a calibration process. A low-power status control command is issued by transmitting signals that include the under-test signal generated by the memory controller to a memory unit to switch the memory unit to a low power status, the low-power status control command forcing the under-test signal to toggle. A read command is issued by the memory controller to the memory unit for reading data. When the responded data does not match the predetermined data, the phase of the under-test signal is determined to be within a timing margin by the memory controller. When the responded data matches the predetermined data, the phase of the under-test signal is determined to be not within the timing margin by the memory controller.

A signal calibration method that includes the steps outlined below is provided. A phase of an under-test signal generated by a memory controller is set to initiate a calibration process. A low-power status control command is issued by transmitting signals that include the under-test signal generated by the memory controller to a memory unit to switch the memory unit to a low power status, the low-power status control command forcing the under-test signal to toggle. A read command is issued by the memory controller to the memory unit for reading data. When the responded data does not match the predetermined data, the phase of the under-test signal is determined to be within a timing margin by the memory controller. When the responded data matches the predetermined data, the phase of the under-test signal is determined to be not within the timing margin by the memory controller.

Disclosed are various embodiments related to stacked memory devices, such as DRAMs, SRAMs, EEPROMs, ReRAMs, and CAMs. For example, stack position identifiers (SPIDs) are assigned or otherwise determined, and are used by each memory device to make a number of adjustments. In one embodiment, a self-refresh rate of a DRAM is adjusted based on the SPID of that device. In another embodiment, a latency of a DRAM or SRAM is adjusted based on the SPID. In another embodiment, internal regulation signals are shared with other devices via TSVs. In another embodiment, adjustments to internally regulated signals are made based on the SPID of a particular device. In another embodiment, serially connected signals can be controlled based on a chip SPID (e.g., an even or odd stack position), and whether the signal is an upstream or a downstream type of signal.

The present disclosure provides a control system and a control method for a double data rate synchronous dynamic random access memory (DDR) system in order to reduce power consumption of the DDR system. The system includes a memory and a processor coupled to the memory, and the processor is configured to monitor a working status of each functional system that shares a power domain with the DDR system, determine a target power parameter value and a target clock parameter value of the DDR system according to the working status of each functional system, and control a power parameter and a clock parameter of the DDR system according to the target power parameter value and the target clock parameter value of the DDR system.