A memory device may include a memory medium and a memory controller. The memory medium may be configured to perform a self-refresh operation and an auto-refresh operation in response to a self-refresh signal and an auto-refresh control signal, respectively. The memory controller may be configured to control the auto-refresh operation by transmitting the auto-refresh control signal to the memory medium. The memory medium includes a self-refresh controller. The self-refresh controller may be configured to control the self-refresh operation based on a self-refresh cycle varying according to an internal temperature of the memory medium and transmit the self-refresh signal to the memory controller. The memory controller may be configured to generate the auto-refresh control signal based on an auto-refresh cycle. The auto-refresh control signal may be determined by the self-refresh signal transmitted from the memory medium.

A high retention time memory element is described that has dual gate devices. A memory element has a write transistor with a gate having a source coupled to a write bit line, a gate coupled to a write line, and a drain coupled to a storage node, wherein a value is written to the storage node by enabling the gate and applying the value to the bit line, and a read transistor having a source coupled to a read line, a gate coupled to the storage node, and a drain coupled to a read bit line, wherein the value of the storage node is sensed by applying a current to the source and reading the sense line to determine a status of the gate.

Methods, systems, and devices for techniques for reducing row hammer refresh are described. A memory device may be segmented into regions based on bits (e.g., the least significant bits) of row addresses such that consecutive word lines belong to different regions. A memory device may initiate a refresh operation for a first row of memory cells corresponding to a first word line. The memory device may determine that the first row is an aggressor row of a row hammer attack and may determine an adjacent row associated with a second word line as a victim row that may need to be refreshed (e.g., to counteract potential data corruption due to a row hammer attack). The memory die may determine whether to perform a row-hammer refresh operation on the victim row based on whether the victim row belongs to a region that is masked.

Apparatuses and methods for targeted row refreshes are disclosed herein. In an example apparatus, a predecoder receives a target row address and determines whether a target row of memory associated with the target row address is a primary or a redundant row of memory. The predecoder is further configured to cause one or more rows of memory physically adjacent the primary row of memory to be refreshed if the primary row is the target row or one or more rows of memory physically adjacent the redundant row of memory to be refreshed if the redundant row of memory is the target row of memory.

The present disclosure includes apparatuses and methods related to compute components formed over an array of storage elements. An example apparatus comprises a base substrate material and an array of memory cells formed over the base substrate material. The array can include a plurality of access transistors comprising a first semiconductor material. A compute component can be formed over and coupled to the array. The compute component can include a plurality of compute transistors comprising a second semiconductor material. The second semiconductor material can have a higher concentration of doping ions than the first semiconductor material.

An apparatus may include an address counter to provide first address information and second address information. The first address information may include a first number of bits and the second address information may include a second number of bits that is smaller than the first number of bits. The address counter may perform a first updating operation. The first updating operation being such that the first address information is updated from a first initial value to a first final value. The address counter may also perform a second updating operation, the second updating operation being such that the second address information is updated from a second initial value to a second final value. In addition, the address counter may also perform the second updating operation at least twice per the first updating operation being performed once.

A memory device includes a memory medium and a memory controller. The memory medium has a memory cell array and may be configured to generate a self-refresh signal, which varies based on an internal temperature of the memory medium, to control a self-refresh operation performed on the memory cell array. The memory controller may be configured to calculate an auto refresh cycle of an auto refresh control signal for controlling an auto-refresh operation of the memory medium based on the self-refresh signal.

A memory storage apparatus having a plurality of operating modes is provided. The memory storage apparatus includes a memory control circuit and a memory cell array circuit. The memory control circuit controls the memory storage apparatus to operate in one of the operating modes. The memory control circuit controls the memory storage apparatus to operate in a first operating mode and controls the memory storage apparatus to switch from the first operating mode to a second operating mode to refresh storage data of the memory cell array circuit. The memory storage apparatus operates in a third operating mode to refresh storage data in the memory storage apparatus. An operating voltage of the memory storage apparatus operating in the second operating mode is smaller than an operating voltage of the memory storage apparatus operating in the third operating mode.

Apparatuses and methods for targeted row refreshes are disclosed herein. In an example apparatus, a predecoder receives a target row address and determines whether a target row of memory associated with the target row address is a primary or a redundant row of memory. The predecoder is further configured to cause one or more rows of memory physically adjacent the primary row of memory to be refreshed if the primary row is the target row or one or more rows of memory physically adjacent the redundant row of memory to be refreshed if the redundant row of memory is the target row of memory.

Methods, systems, and devices for techniques for reducing row hammer refresh are described. A memory device may be segmented into regions based on bits (e.g., the least significant bits) of row addresses such that consecutive word lines belong to different regions. A memory device may initiate a refresh operation for a first row of memory cells corresponding to a first word line. The memory device may determine that the first row is an aggressor row of a row hammer attack and may determine an adjacent row associated with a second word line as a victim row that may need to be refreshed (e.g., to counteract potential data corruption due to a row hammer attack). The memory die may determine whether to perform a row-hammer refresh operation on the victim row based on whether the victim row belongs to a region that is masked.