A memory cell arrangement is provided that may include: at least one memory cell and a read-out circuit. The memory cell includes a first terminal, a second terminal, a third terminal, and a field-effect transistor structure being connected to the first terminal, the second terminal, and the third terminal. The read-out circuit is configured to carry out a read-out operation to read out a memory state of the memory cell, the read-out operation including: providing a first voltage at the first terminal, a second voltage at the second terminal, and a third voltage at the third terminal such that the field-effect transistor structure is in a high-resistivity state and such that a leakage current through the first terminal and/or through the second terminal is generated, and sensing the leakage current to determine the memory state of the memory element.

The present disclosure relates to a flash memory having a plurality of control gates, including: a substrate. An oxide layer disposed on the substrate. A fin-shaped channel layer disposed on the oxide layer, and includes a first end portion, a second end portion, a top surface and two side surfaces, wherein the top surface and the two side surfaces are located between the first end portion and the second end portion, the top surface faces away from the oxide layer and separates the two sides. The two charge storage structures are respectively disposed on the two sides of the fin channel layer. The two gates are disposed on the oxide layer and respectively contact with the two charge storage structures. Two word conductive pillars are connected to the two gates respectively and extending from the two gates in a direction leaving the oxide layer.

Method of operating flash memory unit is provided. Flash memory unit includes first and second split-gate flash memory units, source and drain of first split-gate flash memory unit are connected with first and third bit lines respectively, source and drain of second split-gate flash memory unit is connected with second and third bit line respectively, first control gates of two split-gate flash memory units are connected with first control gate line, second control gates of two split-gate flash memory units are connected with second control gate line, word line gates of two split-gate flash memory units are connected with word line, method includes configuring voltages to first and third bit lines, word line, first and second control gate lines to select first storage bit in first split-gate flash memory unit and make first storage bit in to-be-read or to-be-programmed state; suspending second bit line; reading or programming first storage bit.