Provided herein may be a memory device capable of completing program operations for multiple pages in one ready/busy period. The memory device may include a plurality of memory cells configured to form a plurality of pages, a peripheral circuit configured to perform a first program operation and a second program operation and control logic configured to control the peripheral circuit to receive least significant bit (LSB) page data of a page adjacent to a selected page, center significant bit (CSB) page data, and most significant bit (MSB) page data of the selected page from a memory controller, and program the LSB page data of the page adjacent to the page adjacent to the selected page and to obtain LSB page data from the selected page, previously stored in the selected page, and program the LSB page data, the CSB page data and the MSB page data of the selected page to the selected page.

Technology is disclosed herein for concurrently programming the same data pattern in multiple sets of non-volatile memory cells. Voltage are applied to bit lines in accordance with a data pattern. A select voltage is applied to drain select gates of multiple sets of NAND strings. The system concurrently applies a program pulse to control gates of a different set of selected memory cells in each respective set of the multiple sets of the NAND strings while the select voltage is applied to the drain select gates of the multiple sets of the NAND strings and the voltages are applied to the plurality of bit lines to concurrently program the data pattern into each set of the selected memory cells.

Memory having an array of memory cells might include control logic configured to cause the memory to inhibit memory cells of a first subset of memory cells from programming during each programming pulse of a first plurality of programming pulses and enable those memory cells for programming for at least one programming pulse of a second plurality of programming pulses, inhibit memory cells of a second subset of memory cells from programming during each programming pulse of the second plurality of programming pulses and enable those memory cells for programming for at least one programming pulse of the first plurality of programming pulses, and enable memory cells of a third subset of memory cells for programming during at least one programming pulse of the first plurality of programming pulses and during at least one programming pulse of the second plurality of programming pulses.

Described herein are embodiments related to first-pass dynamic program targeting (DPT) operations on memory cells of memory systems. A method includes determining that a first programming pass of a programming operation has been performed on a memory cell of the memory component, and performing a dynamic program targeting (DPT) operation on the memory cell to calibrate a first program-verify (PV) target value that results in an adjustment to a placement of a first first-pass programming distribution and a second PV target value that results in an adjustment to a placement of a second first-pass programming distribution before a second programming pass of the programming operation is performed on the memory cell.

According to one embodiment, a memory system includes first and second memory chips. The first memory chip has a first plane with a first block and a second block and a second plane with a third block and a fourth block. The second memory chip has a third plane with a fifth block and a sixth block and a fourth plane with a seventh block and an eighth block. The memory controller sets the first and third blocks as a first block unit in a user data storage area and the fifth and seventh blocks as a second block unit in the user data storage area. The memory controller allocates the second block, the fourth block, the sixth block, and the eighth block to a management data storage area. The memory controller manages user data operations for accessing the user data storage area in block units.

A command to program data to a memory device is received. Target charge levels of a set of memory cells in the memory device for a first programming step are determined based on the data. A first set of indicators are provided to the memory device. The first set of indicators indicate the target charge levels for the first programming step. Target charge levels of the set of memory cells for a second programming step are determined based on the data. A second set of indicators are provided to the memory device. The second set of indicators indicate the target charge levels for the second programming step.

Provided herein may be a memory device capable of completing a foggy-fine program operation in one ready/busy period. The memory device may include a plurality of memory cells configured to form a plurality of pages, a peripheral circuit configured to perform a first program operation on a page adjacent to a selected page among the plurality of pages, and perform a second program operation on the selected page and control logic configured to control the peripheral circuit, during the first program operation, to successively receive least significant bit (LSB) page data, center significant bit (CSB) page data, and most significant bit (MSB) page data from a memory controller, and program the LSB page data to the page adjacent to the selected page and during the second program operation, to program the LSB page data programmed to the page adjacent to the selected page, the CSB page data and the MSB page data to the selected page.

A semiconductor storage device includes a first memory die. The first memory die includes a first memory plane including a plurality of first memory blocks, a second memory plane including a plurality of second memory blocks, a first sequencer, and a second sequencer. The first sequencer is configured to start a first write sequence with respect to one of the first memory blocks in response to a first command set designating the one of the first memory blocks if no write sequence is being performed by the first sequencer. The second sequencer is configured to start a second write sequence with respect to one of the second memory blocks in response to a second command set designating the one of the second memory blocks if the first sequencer is performing the first write sequence and no write sequence is being performed by the second sequencer.

Apparatuses and techniques are described for programming data in memory cells while concurrently storing backup data. Initial pages of multiple bit per cell data are encoded to obtain at least first and second pages of single bit per cell data. The initial pages of multiple bit per cell data are programmed into a primary set of memory cells, while concurrently the first and second pages of single bit per cell data are programmed into first and second backup sets of memory cells, respectively. In the event of a power loss, the first and second pages of single bit per cell data are read from the first and second backup sets of memory cells, and decoded to recover the initial pages of multiple bit per cell data.

A memory system includes a plurality of memory cells, and the memory cells are multiple-level cells. The memory system performs program operations to program the memory cells. After each program operation, at least one threshold voltage test is performed to determine if threshold voltages of the memory cells are greater than the verification voltage. When the threshold voltage of a first memory cell is determined to be greater than a first verification voltage, the first memory cell will be inhibited from being programmed during the next program operation. When the threshold voltage of a second memory cell is determined to newly become greater than a second verification voltage, where the second verification voltage is greater than the first verification voltage, the second memory cell will be programmed again during the next program operation.