G11C2211/5623

Multi-state programming for memory devices

Storage device programming methods, systems and media are described. A method may include encoding data to generate an encoded set of data. A first programming operation may write the encoded set of data to a memory device. The method includes encoding, using a second encoding operation based on the data, to generate a second set of encoded data. The second set of encoded data is stored to a cache. A first decoding operation is performed, based on the second set of encoded data and the encoded set of data, to generate a decoded set of data. A second decoding operation is performed to generate a second decoded set of data. The second decoded set of data is encoded to generate a third set of encoded data. The method includes performing a second programming operation to write the third set of encoded data to the memory device.

DYNAMIC PROGRAMMING OF VALLEY MARGINS
20200372962 · 2020-11-26 ·

A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including determining first values of a metric that is indicative of a margin for a valley that is located between programming distributions of a memory cell of the memory device. The operations further include determining second values of the metric based on the first values, and adjusting valley margins of the memory cell in accordance with the second values of the metric.

Multi-State Programming for Memory Devices
20200350007 · 2020-11-05 ·

Storage device programming methods, systems and media are described. A method may include encoding data to generate an encoded set of data. A first programming operation may write the encoded set of data to a memory device. The method includes encoding, using a second encoding operation based on the data, to generate a second set of encoded data. The second set of encoded data is stored to a cache. A first decoding operation is performed, based on the second set of encoded data and the encoded set of data, to generate a decoded set of data. A second decoding operation is performed to generate a second decoded set of data. The second decoded set of data is encoded to generate a third set of encoded data. The method includes performing a second programming operation to write the third set of encoded data to the memory device.

ADJUSTMENT OF PROGRAM VERIFY TARGETS CORRESPONDING TO A LAST PROGRAMMING DISTRIBUTION AND A PROGRAMMING DISTRIBUTION ADJACENT TO AN INITIAL PROGRAMMING DISTRIBUTION
20200286567 · 2020-09-10 ·

A processing device determines difference error counts that are indicative of relative widths of valleys. Each of the valleys is located between a respective pair of programming distributions of a memory cell of the memory component. A program targeting operation is performed on the memory cell to calibrate one or more program verify (PV) targets associated with the programming distributions. To perform the program targeting operation, a rule from a set of rules is selected based on the difference error counts. The set of rules corresponds to an adjusting of a PV target of a programming distribution adjacent to an initial programming distribution. One or more program verify (PV) targets associated with the programming distributions are adjusted based on the selected rule.

DYNAMIC PROGRAMING OF VALLEY MARGINS OF A MEMORY CELL
20200286568 · 2020-09-10 ·

A processing device determines difference error counts for a difference error that is indicative of a margin for a valley that is located between programming distributions of a memory cell of the memory component. A processing device scales each of the plurality of difference error counts by a respective scale factor of the scale factors. The processing device adjusts the valley margins of the memory cell in accordance with the scaled difference error counts.

DRAGGING FIRST PASS READ LEVEL THRESHOLDS BASED ON CHANGES IN SECOND PASS READ LEVEL THRESHOLDS
20200286551 · 2020-09-10 ·

A processing device determines that read level thresholds between first programming distributions of a second programming pass associated the memory component are calibrated. The processing device changes one or more of the read level thresholds between the first programming distributions. The processing device adjusts one or more read level threshold between second programming distributions of a first programming pass based on the change to the one or more read level thresholds between the first programming distributions.

Multi-state programming for memory devices

Storage device programming methods, systems and media are described. A method may include encoding data to generate an encoded set of data. A first programming operation may write the encoded set of data to a memory device. The method includes encoding, using a second encoding operation based on the data, to generate a second set of encoded data. The second set of encoded data is stored to a cache. A first decoding operation is performed, based on the second set of encoded data and the encoded set of data, to generate a decoded set of data. A second decoding operation is performed to generate a second decoded set of data. The second decoded set of data is encoded to generate a third set of encoded data. The method includes performing a second programming operation to write the third set of encoded data to the memory device.

Dynamic programing of valley margins of a memory cell

A processing device determines difference error counts for a difference error that is indicative of a margin for a valley that is located between programming distributions of a memory cell of the memory component. A processing device scales each of the plurality of difference error counts by a respective scale factor of the scale factors. The processing device adjusts the valley margins of the memory cell in accordance with the scaled difference error counts.

CONCURRENT READ AND RECONFIGURED WRITE OPERATIONS IN A MEMORY DEVICE

A method of controlling a memory device can include: receiving, by an interface, a write command from a host; beginning execution of a write operation on a first array plane of a memory array in response to the write command, where the memory array includes a plurality of memory cells arranged in a plurality of array planes; receiving, by the interface, a read command from the host; reconfiguring the write operation in response to detection of the read command during execution of the write operation; beginning execution of a read operation on a second array plane in response to the read command; and restoring the configuration of the write operation after the read operation has at least partially been executed.

MULTI-STATE PROGRAMMING FOR MEMORY DEVICES
20200194064 · 2020-06-18 ·

Storage device programming methods, systems and media are described. A method may include encoding data to generate an encoded set of data. A first programming operation may write the encoded set of data to a memory device. The method includes encoding, using a second encoding operation based on the data, to generate a second set of encoded data. The second set of encoded data is stored to a cache. A first decoding operation is performed, based on the second set of encoded data and the encoded set of data, to generate a decoded set of data. A second decoding operation is performed to generate a second decoded set of data. The second decoded set of data is encoded to generate a third set of encoded data. The method includes performing a second programming operation to write the third set of encoded data to the memory device.