A nonvolatile memory device includes a peripheral circuit region and a memory cell region vertically connected with the peripheral circuit region, the peripheral circuit region including at least one first metal pad, and the memory cell region including at least one second metal pad directly connected with the at least one first metal pad. A method of programming the nonvolatile memory device includes: receiving a programming command, data for a plurality of pages, and an address corresponding to a selected word-line; programming the data for one of the pages to an unselected word-line; reading data of a previously programmed page from the selected word-line; and programming the data for the remaining pages and the data of the previously programmed page to the selected word-line.

A memory device includes a memory cell array and a page buffer circuit, wherein the page buffer circuit includes page buffer units including upper page buffer units and lower page buffer units and cache units arranged between the upper page buffer unit and the lower page buffer units. The cache units include upper cache units and lower cache units. Each page buffer unit includes a sensing node and a pass transistor. The upper cache units share a first combined sensing node, and, the lower cache units share a second combined sensing node. In a data transmission period, sensing nodes respectively included the page buffer units are electrically connected to one another through serial connections of the pass transistors respectively included in the page buffer units.

A device includes an array of memory cells with a first word line coupled to at least a subset of the array of memory cells and control logic coupled to the first word line. The control logic to detect, within a queue, a first read command to read first data from a first page of the subset and a second read command to read second data from a second page of the subset. The control logic is further to cause a voltage applied to the first word line to move to a target value. The control logic is further to cause a page buffer to sense the first data from a first bit line coupled to the first page and to sense the second data from a second bit line coupled to the second page. The control logic is further to cause the first word line to be discharged.

A method of operating a memory system includes programming, in a memory device, K logical pages stored in a page buffer circuit into a memory cell array, reading, from the memory device, the K logical pages programmed into the memory cell array into the page buffer circuit after a first delay time elapses, transmitting, in a memory controller, N−K logical pages to the memory device, and programming, in the memory device, N logical pages into the memory cell array based on the read K logical pages and the N−K logical pages, wherein K is a positive integer and N is a positive integer greater than K.

Based on power on of an electronic device, a location of first data in a NAND flash memory of an electronic device is determined. The first data is transmitted to a shadow RAM of the electronic device, outputting the first data is output from the shadow RAM to a host device of the electronic device through a serial peripheral interface (SPI) when accessing the location of the first data in the NAND Flash memory.

A data transfer circuit in a nonvolatile memory device includes first repeaters, second repeaters and signal lines. The signal lines connect the first repeaters and the second repeaters, and include a first group of signal lines and a second group of signal lines alternatingly arranged. The first repeaters include a first group of repeaters activated in a first operation mode and a second group of repeaters activated in a second operation mode. The second repeaters include a third group of repeaters activated in the first operation mode and are connected to the first group of repeaters through the first group of signal lines floated in the second operation mode, and a fourth group of repeaters activated in the second operation mode and are connected to the second group of repeaters through the second group of signal lines floated in the first operation mode.

A non-volatile memory device includes: a memory cell; a bit line connected to the memory cell; a first cross coupled inverter for storing data sensed from the memory cell through a sensing node connected to the bit line; a first transistor and a second transistor respectively connected to respective ends of the first cross coupled inverter and respectively transmitting a ground voltage to respective ends of the first cross coupled inverter; and a control circuit for operating the first transistor and the second transistor at least once for at least one of an initialize period in which the sensing node is discharged and a precharge period in which the bit line is precharged.

A storage device is provided that allows a controller to directly access bytes of data in data latches connected to memory, as opposed to through controller RAM. The storage device may include a memory, a plurality of data latches connected to the memory, and a controller coupled to each of the data latches. The controller is configured to access one or more bytes of decoded data in one or more of the data latches. For instance, the controller may provide a command including an address for data in the memory, and may process one or more bytes of the data in at least one of the data latches in response to the command. The controller may also store a mapping of addresses for each of the word lines, including the address provided in the command. As a result, operation latency may be reduced and controller RAM savings achieved.

A memory device includes a memory cell array, and a page buffer circuit connected to the memory cell array through a plurality of bit lines, including a plurality of page buffers arranged in correspondence with the bit lines and each of which includes a sensing node. The plurality of page buffers include a first page buffer, and the first page buffer includes: a first sensing node configured to sense data by corresponding to a first metal wire at a lower metal layer; and a second metal wire electrically connected to the first metal wire and at an upper metal layer located above the lower metal layer, and a boost node corresponding to a third metal wire adjacent to the second metal wire of the upper metal layer and configured to control a boost-up and a boost-down of a voltage of the first sensing node.

An operating method of a nonvolatile memory device includes receiving, at the nonvolatile memory device, a suspend command, suspending, at the nonvolatile memory device, a program operation being performed, in response to the suspend command, receiving, at the nonvolatile memory device, a resume command, and resuming, at the nonvolatile memory device, the suspended program operation in response to the resume command. The program operation includes program loops, each of which includes a bit line setup interval, a program interval, and a verify interval. In the program interval of each of the program loops, a level of a program voltage to be applied to selected memory cells of the nonvolatile memory device increases as much as a first voltage. A difference between a level of the program voltage finally applied s suspend and a level of the program voltage applied first after resume is different from the first voltage.