According to one embodiment, a memory system includes a semiconductor memory device including a memory cell capable of holding at least 4-bit data and a controller configured to control a first write operation and a second write operation based on the 4-bit data. The controller includes a conversion circuit configured to convert 4-bit data into 2-bit data. The semiconductor memory device includes a recovery controller configured to recover the 4-bit data based on the converted 2-bit data and data written in the memory cell by the first write operation. The first write operation is executed based on the 4-bit data received from the controller, and the second write operation is executed based on the 4-bit data recovered by the recovery controller.

The present invention discloses a memory reading speed regulating circuit, which uses a reading pulse to trigger an internal flag register to set to 1, and ensures that a data reading operation of a memory reading circuit is completed through a process that a reading operation completed pulse fed back by the memory reading circuit clears the value of the internal flag register to 0; when the reading operation is not completed within specified time, the value of the internal flag register is still 1, and a main controller speeds up the reading speed configuration of the memory reading circuit, and sends a rough regulation operation enable signal again to make a rough regulation judgment. The present invention can reduce the data reading power consumption of the memory and improve the reliability of the data reading operation.

A semiconductor memory device may include: a memory cell array including a plurality of memory cells; a peripheral circuit for performing a program operation on the memory cell array; and a control logic for controlling the peripheral circuit to perform the program operation on the memory cell array. The control logic may control the peripheral circuit to perform a program operation on memory cells included in a selected physical page among the plurality memory cells, in response to a program command, and control the peripheral circuit to perform an additional program operation on at least one memory cell among the memory cells included in the selected physical page, based on whether the program operation has passed.

Circuit designs and operating techniques for a storage device that includes, in one implementation, a memory device including a plurality of memory blocks, each memory block including a plurality of memory cells coupled to a plurality of corresponding word lines; and a memory controller configured to store data in memory cells included in a main area coupled to a selected word line of the plurality of word lines, and store word-line information in a spare area coupled to the selected word line to indicate that a program operation has been performed on the main area.

Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of 5 first memory cells selected simultaneously by a word line. Thereafter, the write circuit writes the data on a second page into the plurality of first memory cell. Then, the write circuit writes the data on the first and second pages into second memory cells adjoining 10 the first memory cells in the bit line direction.

According to one embodiment, three bits stored in one memory cell of a nonvolatile memory correspond to three pages. In first page writing, a threshold voltage becomes within a first or second region base on a bit value. In second page writing, if being within the first region, it becomes within the first or fourth region; and if being within the second region, it becomes within the second or third region. In the third page writing, if being within the first region, it becomes within the first or sixth region; if being within the second region, it becomes within the second or seventh region; if being within the third region, it becomes within the third or eighth region; and if being within the fourth region, it becomes within the fourth or fifth region.

Systems, methods, and apparatus including computer-readable mediums for managing block arrangement of super blocks in a memory such as NAND flash memory are provided. In one aspect, a memory controller for managing block arrangement of super blocks in a memory includes control circuitry coupled to the memory having at least two planes of physical blocks and configured to maintain block information of each individual physical block in the planes and select one or more physical blocks from the planes for a super block based on the block information of the physical blocks in the planes.

A memory chip includes a memory region group including a plurality of memory regions. The memory chip also includes a peripheral unit configured to generate region flags of the memory regions by performing write and read operations on the respective memory regions, each of the region flags indicating whether corresponding memory region is a defective region, and to generate a group flag indicating whether the memory region group needs to be repaired, based on the region flags.

According to one embodiment, a memory system includes a semiconductor memory device including a memory cell capable of holding at least 4-bit data and a controller configured to control a first write operation and a second write operation based on the 4-bit data. The controller includes a conversion circuit configured to convert 4-bit data into 2-bit data. The semiconductor memory device includes a recovery controller configured to recover the 4-bit data based on the converted 2-bit data and data written in the memory cell by the first write operation. The first write operation is executed based on the 4-bit data received from the controller, and the second write operation is executed based on the 4-bit data recovered by the recovery controller.

A method, computer system, and computer program product for operating a computer system to carry out a data dump of a data image of memory contents. Computer operations are temporarily suspended to service the dump request in order to dump the volatile memory contents required for the data image and to generate a record of the non-volatile memory pages which need to be dumped. Computer operations are then resumed under supervision of a monitoring process which screens access requests to the non-volatile memory against the dump record. A request relating to a page contained in the dump record is acted upon by writing the contents of that page to the dump storage space, so the page contents is dumped before it is modified. The dump record in continually updated to keep track of what is still outstanding to complete the dump until such time as the dump is complete.