A semiconductor memory device may include: a memory cell array including a plurality of memory cells; a peripheral circuit for performing a program operation on the memory cell array; and a control logic for controlling the peripheral circuit to perform the program operation on the memory cell array. The control logic may control the peripheral circuit to perform a program operation on memory cells included in a selected physical page among the plurality memory cells, in response to a program command, and control the peripheral circuit to perform an additional program operation on at least one memory cell among the memory cells included in the selected physical page, based on whether the program operation has passed.

According to one embodiment, a semiconductor memory includes a first memory cell array including a plurality of first memory cells; and a second memory cell array including a plurality of second memory cells. Each of threshold voltages of the first memory cells and the second memory cells is set to any of a first threshold voltage, a second threshold voltage higher than the first threshold voltage, and a third threshold voltage higher than the second threshold voltage. Data of three or more bits including a first bit, a second bit, and a third bit is stored using a combination of a threshold voltage of the first memory cell and a threshold voltage of the second memory cell.

A method of verifying the atomicity of an operation of data update in an EEPROM, includes, during a data writing operation of writing the data, the steps of: initializing at least one first flag to a first value and storing this value in the EEPROM; erasing the data from the EEPROM; writing a value of the data into the EEPROM; and writing at least one second value of the first flag into the EEPROM.

According to one embodiment, a memory system includes a semiconductor memory and a controller. The memory system is capable of executing a first operation and a second operation. In the first operation, the controller issues a first command sequence, the semiconductor memory applies a first voltage to a first word line and applies a second voltage to a second word line to read data from the first memory, and the read data is transmitted to the controller from the semiconductor memory. In the second operation, the controller issues a second command sequence, the semiconductor memory applies a third voltage to the first word line and applies a fourth voltage to the second word line, and data held in the memory cell array is left untransmitted to the controller.

A memory controller controls an operation of a semiconductor memory device including a plurality of memory cells at a request of a host. The memory controller includes a data conversion unit. The data conversion unit converts first data from the host by comparing the first data with second data programmed previously.

A nonvolatile memory device performs a compare and write operation. The compare and write operation includes reading read data from memory cells, inverting first write data to generate second write data, adding a first flag bit to the first write data to generate third write data and adding a second flag bit to the second write data to generate fourth write data, performing a reinforcement operation on each of the third write data and the fourth write data to generate fifth write data and sixth write data, and comparing the read data with each of the fifth write data and the sixth write data and writing one of the fifth and sixth write data in the memory cells based on a result of the comparison.

Methods, systems and apparatus for effectively erasing blocks with few programmed pages are provided. In one aspect, a system includes a memory and a controller coupled to the memory. The memory includes blocks each having pages. The controller is configured to determine whether a threshold page with a particular page number in a block of the memory is programmed, to erase the block according to a normal erase action in response to determining that the threshold page is programmed, and to erase the block according to a particular erasing action that is configured to erase the block deeper than the normal erase action in response to determining that the threshold page is not programmed. The particular erasing action can include pre-programming the block before erasing the block, decreasing an erase verify voltage before erasing the block, or adding one or more erasing pulses with a new erasing voltage.

The present invention provides a data processing method for a memory and a related data processor for performing the method. A page of data may be divided into multiple groups. In each group, the number of 1s and the number of 0s are determined, so as to determine whether to reverse or keep the bit data in the group. The encoding scheme may make the bit value 0 more concentrated on the middle states of the state distribution than the bit value 1. The data processor thereby reverses the bit data in a group if the number of 1s is greater than the number of 0s in the group, and keeps the bit data in a group if the number of 1s is less than the number of 0s in the group. As a result, the occurrence probability of the states at two sides becomes lower and the occurrence probability of the middle states becomes higher. This improves data retention of the memory.

Circuit designs and operating techniques for a storage device that includes, in one implementation, a memory device a plurality of memory blocks, each memory block including a plurality of memory cells coupled to a plurality of corresponding word lines; and a memory controller configured to store data in memory cells included in a main area coupled to a selected word line of the plurality of word lines, and store word-line information in a spare area coupled to the selected word line to indicate that a program operation has been performed on the main area.

According to one embodiment, a memory system includes a semiconductor memory and a controller. The memory system is capable of executing a first operation and a second operation. In the first operation, the controller issues a first command sequence, the semiconductor memory applies a first voltage to a first word line and applies a second voltage to a second word line to read data from the first memory, and the read data is transmitted to the controller from the semiconductor memory. In the second operation, the controller issues a second command sequence, the semiconductor memory applies a third voltage to the first word line and applies a fourth voltage to the second word line, and data held in the memory cell array is left untransmitted to the controller.