A three-dimensional integrated circuit includes a first layer including at least one sensing element configured to output at least one temperature-dependent voltage; and a second layer disposed vertically with respect to the first layer and coupled to the first layer by at least one via. The second layer includes: a compare circuit configured to generate at least one intermediate voltage in response to comparing the at least one temperature-dependent voltage to a feedback voltage; a control circuit configured to generate at least one control signal in response to the intermediate voltage; and a switching circuit configured to couple a capacitor coupled to a feedback node to one of a first voltage supply and a second voltage supply in response to the at least one control signal to generate an output signal that is based on a temperature sensed by the sensing element.

A three-dimensional integrated circuit includes a first layer including at least one sensing element configured to output at least one temperature-dependent voltage; and a second layer disposed vertically with respect to the first layer and coupled to the first layer by at least one via. The second layer includes: a compare circuit configured to generate at least one intermediate voltage in response to comparing the at least one temperature-dependent voltage to a feedback voltage; a control circuit configured to generate at least one control signal in response to the intermediate voltage; and a switching circuit configured to couple a capacitor coupled to a feedback node to one of a first voltage supply and a second voltage supply in response to the at least one control signal to generate an output signal that is based on a temperature sensed by the sensing element.

A time domain temperature sensor circuit includes a voltage generating circuit configured to generate and equalize a first voltage of a first node and a second voltage of a second node, a current generating circuit comprising a first semiconductor device connected between the first node and a ground, and configured to generate a first current, and a variable resistor circuit and a second semiconductor device connected in series between the second node and the ground, and configured to generate a second current, the variable resistor circuit being configured to vary a temperature gradient of the second current based on resistance variations by the variable resistor circuit, and a current mirror circuit configured to generate a third current by performing current mirroring of the second current and transmit the third current to an output terminal.

An optimized thermocouple system and a method of optimizing a thermocouple system having a plurality of thermocouple probes and a junction box is provided and includes examining the thermocouple system to identify a first thermocouple probe of the plurality of thermocouple probes, wherein the first thermocouple probe includes a first positive leg and a first negative leg and is located electrically farthest from the junction box. The method includes calculating a first loop resistance between the first thermocouple probe and the junction box and configuring a second thermocouple probe of the plurality of thermocouple probes having a second positive leg, a second negative leg and a second loop resistance such that the second loop resistance is substantially equal to the first loop resistance.

An optimized thermocouple system and a method of optimizing a thermocouple system having a plurality of thermocouple probes and a junction box is provided and includes examining the thermocouple system to identify a first thermocouple probe of the plurality of thermocouple probes, wherein the first thermocouple probe includes a first positive leg and a first negative leg and is located electrically farthest from the junction box. The method includes calculating a first loop resistance between the first thermocouple probe and the junction box and configuring a second thermocouple probe of the plurality of thermocouple probes having a second positive leg, a second negative leg and a second loop resistance such that the second loop resistance is substantially equal to the first loop resistance.

A three-dimensional integrated circuit includes a first layer including at least one sensing element configured to output at least one temperature-dependent voltage; and a second layer disposed vertically with respect to the first layer and coupled to the first layer by at least one via. The second layer includes: a compare circuit configured to generate at least one intermediate voltage in response to comparing the at least one temperature-dependent voltage to a feedback voltage; a control circuit configured to generate at least one control signal in response to the intermediate voltage; and a switching circuit configured to couple a capacitor coupled to a feedback node to one of a first voltage supply and a second voltage supply in response to the at least one control signal to generate an output signal that is based on a temperature sensed by the sensing element.

A three-dimensional integrated circuit includes a first layer including at least one sensing element configured to output at least one temperature-dependent voltage; and a second layer disposed vertically with respect to the first layer and coupled to the first layer by at least one via. The second layer includes: a compare circuit configured to generate at least one intermediate voltage in response to comparing the at least one temperature-dependent voltage to a feedback voltage; a control circuit configured to generate at least one control signal in response to the intermediate voltage; and a switching circuit configured to couple a capacitor coupled to a feedback node to one of a first voltage supply and a second voltage supply in response to the at least one control signal to generate an output signal that is based on a temperature sensed by the sensing element.

An offset corrected bandgap reference and temperature sensor is disclosed. In a complementary metal-oxide-semiconductor (CMOS) bandgap reference, non-idealities in the operational amplifier (op-amp) bandgap reference circuit can lead to a voltage offset. This operational amplifier offset voltage is the dominant source of error in the bandgap reference. If the bandgap reference is used in a temperature sensor, it only needs to be accurate during the analog-to-digital conversion cycle. Embodiments of the present disclosure employ switched capacitors to store the operational amplifier offset during a sample mode in which the bandgap reference operates continuous-time. The operational amplifier offset is then corrected during a hold mode while the temperature sensor completes the analog-to-digital conversion.

An offset corrected bandgap reference and temperature sensor is disclosed. In a complementary metal-oxide-semiconductor (CMOS) bandgap reference, non-idealities in the operational amplifier (op-amp) bandgap reference circuit can lead to a voltage offset. This operational amplifier offset voltage is the dominant source of error in the bandgap reference. If the bandgap reference is used in a temperature sensor, it only needs to be accurate during the analog-to-digital conversion cycle. Embodiments of the present disclosure employ switched capacitors to store the operational amplifier offset during a sample mode in which the bandgap reference operates continuous-time. The operational amplifier offset is then corrected during a hold mode while the temperature sensor completes the analog-to-digital conversion.

A circuit arrangement comprises a first branch comprising a resistor of variable resistance and a diode-connected bipolar transistor and a second branch comprising a resistor of fixed resistance and another diode-connected bipolar transistor. A control loop reproduces a voltage drop at the resistor of variable resistance to a voltage drop at the resistor of fixed resistance. Output terminals are connected to the bipolar transistors to supply a differential voltage. The circuit arrangement may be used as an analog frontend circuit in a gas sensor or a temperature sensor arrangement.