A reduced pin count (RPC) device includes an electrical circuitry in a package with uniformly distributed leads, a subset of the leads being electrically disconnected form the circuitry. A contactor pin block with sockets corresponding to the uniformly distributed leads has the sockets corresponding to the leads with electrical connections filled with test pins suitable for contacting respective leads, and the sockets corresponding to the electrically disconnected leads voided of test pins. Dummy plugs are inserted into the voided sockets to block the sockets and prevent accidental insertions of test pins.

A test apparatus for devices having fine pitches, includes a loading picker provided on one side of a loading part so as to sequentially adsorb devices to be tested, thereby putting the adsorbed devices on the upper surface of a vacuum chuck, a device alignment part, which is provided at an upper portion of a loading zone for aligning the devices, tester for testing a performance of the devices for a set time as the vacuum chuck positioned in the test position moves and comes into electrical contact with bumps of respective devices, and an unloading picker, which is provided at one side of an unloading zone so as to adsorb tested devices from the vacuum chuck, sorts the tested devices into good products and bad products, and unloads the tested devices as sorted on a tray of an unloading part.

An injection device is utilized to inject a liquid onto a test area of a semiconductor element. The injection device includes a height-adjusting base, a reservoir, a first testing pipe, a cleaning pipe, a liquid-draining pipe, and an electrode rod. The reservoir is provided with a dropping port. The dropping port is against the test area of the semiconductor element. The first testing pipe, the cleaning pipe and the liquid-draining pipe are connected to the reservoir. The electrode rod penetrates through the reservoir and contacts and ionizes a testing liquid. A semiconductor testing system utilizing the injection device and its testing method are also provided herein.

A test apparatus and an automatic test equipment having the same are disclosed. The test apparatus includes a test head having a test area, a socket board combined to the test area of the test, the socket board including a socket body and an active device attached on a first surface of the socket body, the active device configured to operate a semiconductor package, and a heat exchanger arranged on an upper portion of the test head, the heat exchanger being in contact with the socket board.

According to a certain embodiment, a pin plunger includes: a first contact member; a second contact member that faces the first contact member and is apart from the first contact member; a spring arranged between the first contact member and the second contact member; and a housing that houses the first contact member, the second contact member, and the spring. The housing comprises a bimetal inside or outside the housing. The bimetal comprises a first metal and a second metal, the first metal having a thermal expansion coefficient different from a thermal expansion coefficient of the second metal. The elastic force decreased or increased by contracting or expanding of the spring due to a temperature change is compensated with a warping force due to stretching of the first metal and the second metal.

Embodiments provided herein include methods, compositions, and uses of aromatic alcohols to increase the potency of antifungal agents.

A testing apparatus for a semiconductor package includes a circuit board, testing patterns and a socket. The circuit board has a testing region and includes a plurality of testing contacts and a plurality of signal contacts distributed in the testing region. The testing patterns are embedded in the circuit board and electrically connected to the testing contacts, where each of the testing patterns includes a first conductive line and a second conductive line including a main portion and a branch portion connected to main portion. The first conductive line is connected to the main portion. The socket is located on the circuit board and comprising connectors electrically connected to the circuit board, wherein the connectors are configured to transmit electric signals for testing the semiconductor package from the testing apparatus.

An apparatus for testing a package-on-package type semiconductor package includes an upper test socket on which an upper package is mounted, the upper test socket being mounted on a pusher and connected to the lower package; a lower test socket mounted on a tester and connected to the lower package; and an adsorption pad coupled to the pusher and configured to adsorb and pressurize the lower package using a vacuum pressure, wherein the adsorption pad comprises a body part having a vacuum pressure passage formed therein; and an adsorption part having an adsorption hole corresponding to the vacuum pressure passage, and the body part is attached on a central portion of an upper surface of the adsorption part and an outer oil overflow-preventing part configured to trap silicon oil eluted from the body part is formed at an outer periphery the adsorption part.

The present disclosure relates to a test apparatus for a package-on-package type semiconductor package including a lower test socket mounted on a tester, and connected to a lower package to electrically connect the lower package to the tester; a pusher configured to be able to be moved vertically by receiving a driving force from a driving unit; an upper test socket mounted on the pusher, and having an electro-conductive part installed below the upper package to be electrically connected to the upper package; a vacuum picker mounted on the upper test socket to be able to vacuum-adsorb the lower package; and an inelastic insulating sheet installed between the upper test socket and the upper package, having a through hole formed at a position thereof corresponding to the terminal of the upper package and the electro-conductive part.

A method includes forming a plurality of dielectric layers, forming a plurality of redistribution lines in the plurality of dielectric layers, etching the plurality of dielectric layers to form an opening, filling the opening to form a through-dielectric via penetrating through the plurality of dielectric layers, forming a dielectric layer over the through-dielectric via and the plurality of dielectric layers, forming a plurality of bond pads in the dielectric layer, bonding a device die to the dielectric layer and a first portion of the plurality of bond pads through hybrid bonding, and bonding a die stack to through-silicon vias in the device die.