A circuit chip is connected to a sensor chip in a sub-unit via a communication terminal, and includes an output wave formation circuit that performs communication by controlling a voltage of a power supply supplied from an electronic control unit (ECU) to raise a voltage level of an output signal. When the voltage of the power supply monitored by a voltage monitor rises above a threshold value, a control circuit lowers a voltage of a signal from the output wave formation circuit, thereby preventing an excessive rise of the power supply voltage used in a signal communication.

A power capability determination device is arranged to determine a power capability of a power source, and includes a connector, a load circuit, a switch circuit, a voltage monitor circuit, and a processing circuit. The connector is arranged to receive the power source to output an input voltage at a power output terminal. The switch circuit is electrically connected between the load circuit and the power output terminal. The voltage monitor circuit is electrically connected to the power output terminal, and is arranged to monitor the input voltage to generate a monitored voltage value. The processing circuit is electrically connected to the voltage monitor circuit and the switch circuit, and is arranged to control the switch circuit, and in a state of controlling the switch circuit, receive the monitored voltage value and determine the power capability of the power source according to the monitored voltage value.

During normal operation of a processor, voltage droop is likely to occur and there is, therefore, a need for techniques for rapidly and accurately detecting this droop so as to reduce the probability of circuit timing failures. The droop detector described herein uses a tap sampled delay line in which a clock signal is split along two separate paths. Each of the taps in the paths are separated by two inverter delays such that the set of samples produced represent sample values of the clock signal that are each separated by a single inverter delay without inversion of the first clock signal between the samples.

Disclosed herein are related to an integrated circuit to regulate a supply voltage. In one aspect, the integrated circuit includes a metal rail including a first point, at which a first functional circuit is connected, and a second point, at which a second functional circuit is connected. In one aspect, the integrate circuit includes a voltage regulator coupled between the first point of the metal rail and the second point of the metal rail. In one aspect, the voltage regulator senses a voltage at the second point of the metal rail and adjusts a supply voltage at the first point of the metal rail, according to the sensed voltage at the second point of the metal rail.

In accordance with an embodiment, a circuit includes a plurality of comparators disposed on an integrated circuit, the plurality of comparators having inputs coupled to a monitored power supply line; and a voting circuit having inputs coupled to outputs of the plurality of comparators. An output of the voting circuit is configured to provide a signal indicative of a brown out condition of a power source coupled to the monitored power supply line.

A system and method for measuring power supply variations are described. A functional unit includes one or more power supply monitors capable of measuring power supply variations. The power supply monitors forego use of a clock signal from clock generating circuitry and forego use of a reference voltage from a reference power supply. The power supply monitors use an output of a source ring oscillator as a clock signal for the sequential elements of a counter. The counter measures a number of revolutions of a measuring ring oscillator within a period of the output of the source oscillator. The revolutions of the measuring ring oscillator are associated with a number of rising edges and falling edges of the output signal of the measuring ring oscillator. An encoder converts the output of the sequential elements to a binary value, and sends the binary value to an external age tracking unit.

An electronic device includes a driver that is connected with a pin, receives an input signal, and outputs an output signal to the pin in response to the input signal, a core circuit that transfers the input signal to the driver, and a monitor circuit that receives the input and output signals and detects a stuck voltage state of the output signal based on the input and output signals. The monitor circuit includes a first detection circuit that detects the stuck voltage state when the input and output signals are logically incorrect, a second detection circuit that detects the stuck voltage state when the input and output signals are logically correct and when the output signal is at a low level, and a third detection circuit that detects the stuck voltage state when the input and output signals are logically correct and when the output signal is at a high level.

A semiconductor device 1 includes: a first oscillator 11_RC1 configured to operate at a detected voltage, the first oscillator having first temperature dependency; a second oscillator 11_RC4 configured to operate at the detected voltage, the second oscillator having second temperature dependency; a count unit configured to count an output of the first oscillator and an output of the second oscillator, the output of the first oscillator and the output of the second oscillator being supplied to the count unit; an arithmetic unit configured to calculate a count value CNT (T1) of the first oscillator and a count value CNT (T4) of the second oscillator, the count values of the first and second oscillators being counted by the count unit; and a determining unit configured to compare an output of the arithmetic unit with a threshold value to output a detected result signal corresponding to a result of the comparison.

During normal operation of a processor, voltage droop is likely to occur and there is, therefore, a need for techniques for rapidly and accurately detecting this droop so as to reduce the probability of circuit timing failures. The droop detector described herein uses a tap sampled delay line in which a clock signal is split along two separate paths. Each of the taps in the paths are separated by two inverter delays such that the set of samples produced represent sample values of the clock signal that are each separated by a single inverter delay without inversion of the first clock signal between the samples.

A semiconductor chip includes a semiconductor device connected between a first node to which a power supply voltage is applied and a second node to which a ground voltage is applied, a first ring oscillator connected to the first node through a first supply switch and the second node through a first ground switch and a second ring oscillator connected to the first node through a second supply switch and the second node through a second ground switch, wherein the first supply and ground switches are configured to operate in response to a first control signal, thereby operating the first ring oscillator, and the second supply and ground switches are configured to operate in response to a second control signal, thereby operating the second ring oscillator.