An apparatus for detecting noise in a power supply of a PLC analog input/output module is provided. The apparatus may include a capacitor configured to extract a noise determination target voltage from a driving voltage outputted from the power supply; a voltage conversion unit configured to convert the noise determination target voltage outputted from the capacitor and to output the converted noise determination target voltage; a comparison unit configured to compare the noise determination target voltage converted by the voltage conversion unit with a reference voltage; and a determination unit configured to determine whether the noise determination target voltage is a noise, based on a comparison result by the comparison unit.

A system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is to perform operations including detecting a voltage of a power source for the memory device has dropped below a threshold voltage indicative of an imminent power loss and writing data to the memory device in response to the detecting. The operations further include measuring a characteristic of the data in response to detecting a power on of the memory device; determining an estimated amount of time for which the memory device was powered off based on results of the measuring; and in response to the estimated amount of time satisfying a first threshold criterion, updating a value for a temporal voltage shift of a block family of programmed data based on the estimated amount of time.

The abnormal power supply voltage detection device has a function of accurately detecting the abnormal voltage in accordance with the characteristics of the semiconductor element for each semiconductor chip. Circuit group for operating the adjustment function has a function of preventing the influence of the power supply voltage of the logic system such as control in the semiconductor product malfunctions becomes abnormal. Furthermore, it has a function of detecting the abnormal voltage of the various power supplies in the semiconductor product. It also has a function to test the abnormal voltage detection function in the normal power supply voltage range during use of semiconductor products.

Disclosed are methods and circuits to measure independently of duty cycles a pulsed current of a pass transistor of a switched circuit. Methods and circuits of one embodiment may be applied to precisely operate DC-to-DC converters such as buck converters in the most efficient operation modes. Another embodiment can be used to measure the pulsed current independently of duty cycle over a wide range of current values.

Disclosed is a power failure detection circuit, including a first PMOS FET (mp1), a second PMOS FET (mp2), a first NMOS FET (mn2), a second NMOS FET (mn3) and a reset transistor (mn1). The PN junction area of the drain electrode of the first PMOS FET (mp1) is greater than the PN junction area of the drain electrode of the first NMOS FET (mn2). The PN junction area of the drain electrode of the second NMOS FET (mn3) is greater than the PN junction area of the drain electrode of the second PMOS FET (mp2). The power failure detection circuit of the present invention is novel in design and high in practicability.

First and second output transistors are connected in series between a power supply terminal and a ground terminal through an output node connected to an output terminal. An output transistor control circuit is arranged corresponding to at least one of the first and second output transistors and is configured to input a voltage at the output terminal to the gate of the first output transistor at a time of occurrence of disconnection of the power supply terminal and input the same to the gate of the second output transistor at a time of occurrence of disconnection of the ground terminal. The first output transistor has a conductivity type to turn off when a power supply voltage is input to the gate, and the second output transistor has a conductivity type to turn off when a ground voltage is input to the gate.

Some examples described herein provide for an on-die virtual probe in an integrated circuit structure for measurement of voltages. In an example, an integrated circuit comprises a voltage-controlled frequency oscillator circuitry and a processor circuitry. The voltage-controlled frequency oscillator circuitry comprises a plurality of circuitry components and is configured to generate a signal having a frequency related to a supply voltage. The voltage-controlled frequency oscillator circuitry is disposed at a location of the integrated circuit proximal to the supply voltage being monitored. The processor circuitry is configured to identify a relationship between the frequency of the signal and the supply voltage. The processor circuitry is also configured to determine a value of the supply voltage associated with the signal based on the identified relationship. The processor circuitry further monitors on-die transient voltages at the location of the integrated circuit based on the value of the supply voltage.

A semiconductor device 1 includes: a first oscillator 11_RC1 configured to operate at a detected voltage, the first oscillator having first temperature dependency; a second oscillator 11_RC4 configured to operate at the detected voltage, the second oscillator having second temperature dependency; a count unit configured to count an output of the first oscillator and an output of the second oscillator, the output of the first oscillator and the output of the second oscillator being supplied to the count unit; an arithmetic unit configured to calculate a count value CNT (T1) of the first oscillator and a count value CNT (T4) of the second oscillator, the count values of the first and second oscillators being counted by the count unit; and a determining unit configured to compare an output of the arithmetic unit with a threshold value to output a detected result signal corresponding to a result of the comparison.

A low voltage detection circuit includes a first detection block configured to detect a level of an external voltage according to a reference voltage, and output a pre-detection signal; and a second detection block configured to generate a low voltage detection signal of a beginning level regardless of a variation in a level of the pre-detection signal when the level of the pre-detection signal is detected as the beginning level.

A self-referenced on-die voltage droop detector generates a reference voltage from the supply voltage of an integrated circuit's power distribution network, and compares this reference voltage to the transient supply voltage in order to detect voltage droops. The detector responds to detected occurrences of voltage droop with low latency by virtue of being located on-die. Also, by generating the reference voltage from the integrated circuit's power domain rather than using a separate reference voltage source, the detector does not introduce noise and distortion associated with a separate power domain.