The present disclosure relates to a detection circuit 200 for detecting oscillations of a regulated supply signal 110. The detection circuit includes a filter circuit 210 to filter the regulated supply signal in order to obtain a filtered supply signal 212. A peak value detector circuit 220 is designed to detect an extreme value of the filtered supply signal. A comparator circuit 230 is designed to compare the detected extreme value with a threshold value and to indicate an understepping or exceedance of the threshold value.

Disclosed herein is a voltage comparator including a first capacitor, a first inverter and a first switch connected in series and provided between both ends of the first capacitor, a second inverter connected in parallel with the first inverter, a second switch provided between an input and an output of the first inverter, a third switch provided between an input and an output of the second inverter, a second capacitor provided between the output of the first inverter and the input of the second inverter, a third capacitor provided between the output of the second inverter and the input of the first inverter, and a fourth switch provided in one of a position between an upper electrode of the first capacitor and a power supply line and a position between a lower electrode of the first capacitor and a ground line.

Aspects of the invention include a circuit having a power supply sensitive delay circuit, a variable delay circuit coupled to the power supply sensitive delay circuit, a delay line coupled to the variable delay circuit, and a logic circuit coupled to the delay line.

Disclosed herein are related to an integrated circuit to regulate a supply voltage. In one aspect, the integrated circuit includes a metal rail including a first point, at which a first functional circuit is connected, and a second point, at which a second functional circuit is connected. In one aspect, the integrate circuit includes a voltage regulator coupled between the first point of the metal rail and the second point of the metal rail. In one aspect, the voltage regulator senses a voltage at the second point of the metal rail and adjusts a supply voltage at the first point of the metal rail, according to the sensed voltage at the second point of the metal rail.

An undervoltage detection circuit includes a voltage divider, a voltage-to-current (V-to-I) converter and a current comparator. The voltage divider divides a supply voltage to generate a divided voltage. The V-to-I converter converts the divided voltage into a first current based on a first V-to-I transfer function, and converts the divided voltage into a second current based on a second V-to-I transfer function different from the first V-to-I transfer function. The current comparator compares the first and second currents to generate a comparison signal that indicates whether the supply voltage is sufficiently large.

A digital circuit device includes a power supply circuitry, a digital circuitry, a digital circuitry, and a protection circuitry. The power supply circuitry is configured to output a supply voltage. The digital circuitry is configured to be driven by the supply voltage, and is configured to perform at least one operation according to a first clock signal. The protection circuitry is configured to generate the first clock signal according to at least one of a voltage drop of the supply voltage and a load signal sent from the digital circuitry.

Examples of an electronic component device includes a housing formed of a member that causes radiation to lose its energy by generating an electric charge when the housing is subjected to the radiation and an electronic component housed in the housing. The member is a semiconductor device member having a PN junction.

A method and device for avoiding abnormal signal oscillation in UVLO test, applied to a power supply module, includes: a voltage detection module (301) detecting a voltage of an enable terminal of the power supply module during an under voltage lock out UVLO test; a difference calculation module (302) calculating a difference value between a detected voltage and a voltage trigger threshold of the enable terminal; upon a control module (303) determining that the difference value is below a preset first threshold, the control module increasing the voltage of the enable terminal during UVLO test via a voltage adjustment module. The application of the above solution of the present application can avoid abnormal signal oscillation in UVLO test.

A memory sub-system includes a power management integrated circuit (PMIC) compatible with operation at an uppermost PMIC supply voltage that is lower than a primary supply voltage of the memory sub-system. The PMIC is configured to output multiple voltages for operation of the memory sub-system based on a PMIC supply voltage. The memory sub-system further includes a capacitive voltage modifier (CVM) coupled to the PMIC. The CVM is configured to receive the primary supply voltage of the memory sub-system as an input and provide a first modified primary supply voltage (MPSV) to the PMIC as the PMIC supply voltage, where the first MPSV is not higher than the uppermost PMIC supply voltage.

An integrated circuit (IC) includes subcircuits, power switches coupled to pass load current to a respective one of the subcircuits when activated by a respective switch control signal, and sensing circuits. Each of the sensing circuits is coupled to a respective one of the subcircuits, wherein the sensing circuits are configured to generate sense currents that are proportional to the respective load currents. The IC also includes a conversion circuit configured to receive at least one of the sense currents and to convert the at least one of the sense currents to an equivalent multi-bit digital signal, a timestamp circuit configured to generate a timestamp value that is correlated with the multi-bit digital signal, and a controller configured to provide signals to operate the power switches and the sensing circuits.