The invention relates to a high-voltage dry apparatus having a semiconductor layer (2) covered by a metal screen (3), this screen (3) being eliminated so as to expose this semiconductor layer (2) over a length, this cable being connected to an element of equipment having an outer envelope (6) mechanically connected to said screen. According to the invention, an electronic monitoring arrangement (20) is contained within said envelope (6), this electronic arrangement (20) being electrically connected to an electrical power supply arrangement (21) surrounding said semiconductor layer (2) and to the metal screen (3) of said cable on either side of said length of the exposed semiconductor layer.

A system and method for stress-testing of electronic components are disclosed. The system and method include a stationary bath including a tub that defines an aperture in a plane, in which a plurality of slots are positionable and defined inside the tub and oriented orthogonally with respect to the plane. A dielectric fluid in the tub is heated by a heating element to a predetermined temperature value. A board is configured to be retrievably placed with one of the plurality of slots, the board having a plurality of sockets operable to receive corresponding electronic components.

[Object] To provide a semiconductor device capable of improving a discharge starting voltage when measuring electric characteristics, and widening a pad area of a surface electrode or increasing the number of semiconductor devices (number of chips) to be obtained from one wafer, and a method for manufacturing the same.

[Solution Means] A semiconductor device 1 includes an n-type SiC layer 2 having a first surface 2A, a second surface 2B, and end faces 2C, a p-type voltage relaxing layer 7 formed in the SiC layer 2 so as to be exposed to the end portion of the first surface 2A of the SiC layer 2, an insulating layer 8 formed on the SiC layer 2 so as to cover the voltage relaxing layer 7, and an anode electrode 9 that is connected to the first surface 2A of the SiC layer 2 through the insulating layer 8 and has a pad area 95 selectively exposed.

A test key and a method for monitoring a semiconductor wafer are disclosed. The test key includes a first testing unit and a second testing unit. The first testing unit has a first diode-to-conductive layer area ratio. The second testing unit has a second diode-to-conductive layer area ratio. The second diode-to-conductive layer area ratio is smaller than the first diode-to-conductive layer area ratio.

A direct current (DC) fault arc detection method, including performing sampling, filtering and fast Fourier transform (FFT) on an input current of a high frequency power electronics converter, to obtain an amplitude-frequency characteristic curve of a current high frequency component; and selecting, from the amplitude-frequency characteristic curve, at least one frequency band including a switching frequency or a multiple frequency, calculating a peak value D1 of amplitudes and an average value D2 of the amplitudes within the frequency band, and determining, according to a change of a distance between the peak value D1 and the average value D2, whether an arc occurs, where if the average value D2 approaches the peak value D1, an arc occurs; otherwise, no arc occurs.

A semiconductor wafer includes dielectric regions of different thicknesses, some of the dielectric regions being thinner and other ones of the dielectric regions being thicker. The semiconductor wafer further includes a stress circuit operable to stress at least one of the dielectric regions internally within the semiconductor wafer for assessing dielectric reliability. A corresponding method of internally assessing dielectric reliability of a semiconductor technology is also provided.

An exemplary apparatus includes a testing module connected to, and providing a test voltage to, an integrated circuit containing devices under test. The testing module performs a time-dependent dielectric breakdown (TDDB) test on the devices under test. A decoder is connected to the devices under test and the testing module. The decoder selectively connects each device being tested to the testing module. Efuses are connected to a different one of the devices under test. The efuses separately electrically disconnect each of the devices under test from the test voltage upon failure of a corresponding device under test. Protection circuits are connected between the efuses and a ground voltage. Each protection circuit provides a shunt around the decoder upon failure of the device under test.

[Object] To provide a semiconductor device capable of improving a discharge starting voltage when measuring electric characteristics, and widening a pad area of a surface electrode or increasing the number of semiconductor devices (number of chips) to be obtained from one wafer, and a method for manufacturing the same. [Solution Means] A semiconductor device 1 includes an n-type SiC layer 2 having a first surface 2A, a second surface 2B, and end faces 2C, a p-type voltage relaxing layer 7 formed in the SiC layer 2 so as to be exposed to the end portion of the first surface 2A of the SiC layer 2, an insulating layer 8 formed on the SiC layer 2 so as to cover the voltage relaxing layer 7, and an anode electrode 9 that is connected to the first surface 2A of the SiC layer 2 through the insulating layer 8 and has a pad area 95 selectively exposed.

A test key and a method for monitoring a semiconductor wafer are disclosed. The test key includes a first testing unit and a second testing unit. The first testing unit has a first diode-to-conductive layer area ratio. The second testing unit has a second diode-to-conductive layer area ratio. The second diode-to-conductive layer area ratio is smaller than the first diode-to-conductive layer area ratio.

A direct current (DC) fault arc detection method, including performing sampling, filtering and fast Fourier transform (FFT) on an input current of a high frequency power electronics converter, to obtain an amplitude-frequency characteristic curve of a current high frequency component; and selecting, from the amplitude-frequency characteristic curve, at least one frequency band including a switching frequency or a multiple frequency, calculating a peak value D1 of amplitudes and an average value D2 of the amplitudes within the frequency band, and determining, according to a change of a distance between the peak value D1 and the average value D2, whether an arc occurs, where if the average value D2 approaches the peak value D1, an arc occurs; otherwise, no arc occurs.