Provided are a charge trap evaluation method and semiconductor device including, in an embodiment, a step for applying an initialization voltage that has the same sign as a threshold voltage and is greater than or equal to the threshold voltage between the source electrode 15 and drain electrode 16 of a semiconductor device 1 having an HEMT structure and the substrate 10 of the semiconductor device 1 and initializing a trap state by forcing out trapped charge from a trap level and a step for monitoring the current flowing between the source electrode 15 and drain electrode 16 after the trap state initialization and evaluating at least one from among charge trapping, current collapse, and charge release.

A monitoring device is provided for monitoring a semiconductor-based switching element having a control input, a power input, and a power output. The monitoring device includes a charge carrier source for charging the control input of the switching element with electric charge carriers, and a measuring device for detecting a charge carrier drain from the control input of the switching element. The measuring device emits a warning signal if the charge carrier drain lies above a specified threshold value. A corresponding method for monitoring a semiconductor-based switching element is also provided.

A system can include a plurality of device under test (DUT) cells. Each DUT cell can include a DUT and a plurality of switches configured to control a flow of current to the DUT. The system can further include a controller configured to execute a plurality of test to the plurality of DUTs in the plurality of DUT cells. Each of the plurality of tests comprises applying a measurement condition to a given DUT of the plurality of DUTs and concurrently applying a stress condition to the remaining DUTs of the plurality of DUTs, wherein the plurality of tests can provide measurements sufficient to determine a bias thermal instability and a time dependent dielectric breakdown of the given DUT.

Spike safe floating current and voltage source (VI) containing a forced voltage amplifier in series with a selectable resistor. A method of providing a VI with forced current testing mode using a forced voltage amplifier in series with a selectable resistor. A method of providing a VI with forced voltage testing mode using a forced voltage amplifier in series with a selectable resistor. A method of measuring the on resistance of a device under test using a VI with a forced voltage amplifier in series with a selectable resistor. A method of measuring the breakdown of an input/output junction of a device under test using a VI with a forced voltage amplifier in series with a selectable resistor.

The present application discloses a method and apparatus for calculating the kink current of SOI device, which is used to solve the problem that the kink current calculation in the prior art is not accurate and is not suitable for circuit simulation. The method includes: obtaining the impact ionization factor, the parasitic transistor effect factor, and the drain saturation current of the SOI device respectively; and calculating the kink current of the SOI device according to the impact ionization factor, the parasitic transistor effect factor, and the drain saturation current.

Test structures for a body-contacted field effect transistor (BCFET) include: a single-pad structure with body contact and probe pad regions connected to a channel region at first and second connection points with a known separation distance between the connection points; and a multi-pad structure with a body contact region connected to a channel region at a first connection point and multiple probe pad regions connected to the channel region at second connection points that are separated from the first connection point by different separation distances. A method includes: determining separation distance-dependent internal body potentials at the second connection points in response to different bias conditions by using either multiple single-pad structures, each having a different separation distance between the connection points, or by using a multi-pad structure; and based on the separation distance-dependent internal body potentials, generating a model representing the BCFET with body-contacted and floating body devices.

A testing system includes: a substrate having a probe pad and having a supply input; driver circuitry having a driver output; a transistor having a gate, a source, and a drain; and a field effect transistor (FET) engager. The gate of the transistor is coupled to the driver output, and the drain of the transistor is coupled to the supply input. The FET engager is configured to couple the probe pad to the gate of the transistor and provide test instrument measurement of gate current of the transistor without test instrument probe capacitance impacting operation of the transistor.

A testing circuit includes a first circuit and a second circuit. The first circuit and second circuit have a first capacitor and a second capacitor. The first circuit is connected to a first transistor. The second circuit is connected to a second transistor. A first inductor has a first terminal connected to an input of the testing circuit and a second terminal connected to a source of the second transistor. A first diode has an anode connected to ground and a cathode connected to the second terminal of the first inductor. The second capacitor has a first terminal connected to a drain of the second transistor and a second terminal connected to ground. The first capacitor has a first terminal connected to the input of the testing circuit and a second terminal connected to ground.

For example, a method of measuring a device parameter includes: a step of repeatedly measuring the gate-source voltage (or gate-emitter voltage) of a switching element in its switching transient state while switching the external gate resistance for the switching element among m resistance values (where m is an integer of three or more); and a step of, while representing the internal gate resistance and the plateau voltage of the switching element by Rgin and Vp respectively and using the m resistance values of the external gate resistance and corresponding m voltage values of the gate-source voltage (or gate-emitter voltage) as Rg(k) and Vgs(k) respectively (where k=1, 2 . . . m), performing the fitting of the equation Vgs(k)=Rg(k)/(Rg(k)+Rgin)×Vp, thereby to derive the internal gate resistance Rgin or the plateau voltage Vp of the switching element.

A method is provided to increase processor frequency in an integrated circuit (IC). The method includes identifying a gate included in the IC, the gate having a gate threshold voltage and performing a plasma process to form an antenna signal path in signal communication with the gate. The method further comprises adjusting the plasma process or circuit design to increase plasma induced damage (PID) applied to the gate so as to alter the gate threshold voltage.