A probe card with a voltage terminal configured to be coupled to a voltage supply and a current terminal configured to be coupled to a current supply. The voltage terminal and the current terminal are configured to be coupled to an input node of a device under test (DUT) field effect transistor (FET) through probe needles. The probe card has an overlap resistor capacitor (RC) element coupled to the input node. The probe card includes an analog to digital (ADC) voltage capture module configured to be coupled to the input node of the DUT FET and to an output node of the DUT FET through the probe needles. The probe card has a resistive element configured to be coupled to the output node of the DUT FET through the probe needles and to an electrically neutral node and an ADC current capture module coupled in parallel to the resistive element.

Disclosed is a measuring device and a method for measuring a dielectric value of a fill substance. The measuring device includes a signal production unit for driving a transmitting unit to transmit a radar signal toward the fill substance; a receiving unit for receiving of the radar signal; and an evaluation unit to ascertain an amplitude of the received signal, a phase shift, and/or a signal travel time of the radar signal. Based on the signal travel time, the phase shift, and/or the ascertained amplitude, the dielectric value can be determined. The transmitting unit and the receiving unit comprise at least two radiating elements arranged relative to one another in a corresponding number of rows. Because of a per row increasing phase delay, the measuring range over which the dielectric value can be determined is increased.

A semiconductor test apparatus according to the present disclosure includes: a stage on which a wafer is to be mounted; a pressurizing wall disposed on a surface of a probe card opposing the stage, extending toward the stage, and having an opening; a mark disposed on a lower surface of the pressurizing wall opposing the stage; a probe disposed in the opening; an air tube to force air into the opening; a detector to detect first spacing between a tip of the probe and the mark; and a controller to control second spacing between the wafer and the lower surface of the pressurizing wall based on the first spacing, wherein, when an electrical property of each of chips of the wafer is measured, the second spacing is controlled to be predetermined spacing by the controller, and the air is forced into the opening through the air tube.

One example includes a method for surge-testing a gallium nitride (GaN) transistor device-under-test (DUT) that includes at least one GaN transistor device. The method includes inserting the GaN transistor DUT into a test fixture comprising an inductor such that the inductor is coupled to the GaN transistor device to form a switching power regulator. The method also includes operating the switching power regulator at a DUT operating voltage to generate an output current through the inductor based on a DUT input voltage and a duty-cycle. The method also includes controlling an excitation voltage source to provide a voltage surge-strike to the GaN transistor DUT. The method also includes measuring the output current and the DUT input voltage at least one of during and after the voltage surge-strike. The method further includes storing the measured output current and the measured DUT input voltage in a memory to specify device characteristics of the GaN transistor DUT.

A method is provided to increase processor frequency in an integrated circuit (IC). The method includes identifying a gate included in the IC, the gate having a gate threshold voltage and performing a plasma process to form an antenna signal path in signal communication with the gate. The method further comprises adjusting the plasma process or circuit design to increase plasma induced damage (PID) applied to the gate so as to alter the gate threshold voltage.

A testing circuit includes a first circuit and a second circuit. The first circuit and second circuit have a first capacitor and a second capacitor. The first circuit is connected to a first transistor. The second circuit is connected to a second transistor. A first inductor has a first terminal connected to an input of the testing circuit and a second terminal connected to a source of the second transistor. A first diode has an anode connected to ground and a cathode connected to the second terminal of the first inductor. The second capacitor has a first terminal connected to a drain of the second transistor and a second terminal connected to ground. The first capacitor has a first terminal connected to the input of the testing circuit and a second terminal connected to ground.

A field effect transistor (FET) engager, for example, includes electrically coupling a gate driver to a gate of a FET for testing the FET. The FET engager further includes providing a probe pad for test instrument measurement of the FET without test instrument capacitance impacting operation of the FET. The FET engager can electrically couple to the gate of the FET hold the gate of the FET at a low voltage while the source and drains are stress tested. The FET engager provides fail-safe mechanisms against accidental turn-on of the FET during operation. The FET engager can provide a second probe pad for selective test instrument turn-on of a second FET. The FET engager can allow test instrument measurement of gate current of the FET without test instrument capacitance impacting operation of the FET.

The present application discloses a method and apparatus for calculating the kink current of SOI device, which is used to solve the problem that the kink current calculation in the prior art is not accurate and is not suitable for circuit simulation. The method includes: obtaining the impact ionization factor, the parasitic transistor effect factor, and the drain saturation current of the SOI device respectively; and calculating the kink current of the SOI device according to the impact ionization factor, the parasitic transistor effect factor, and the drain saturation current.

A testing circuit includes a first circuit and a second circuit. The first circuit has a first capacitor and a second capacitor. The first circuit is configured to transfer at least a portion of a first voltage across the first capacitor to the second capacitor. The second circuit has the first capacitor and the second capacitor. The second circuit is configured to transfer at least a portion of a second voltage across the second capacitor to the first capacitor.

A test system, a method for manufacturing an electronic device, and a method for testing a wafer or electronic device that includes coupling a transistor in a series circuit with a capacitor and a resistor, coupling a voltage source to the capacitor to charge the capacitor to a non-zero DC voltage while the transistor is turned off, disconnecting the voltage source from the capacitor while the transistor is turned off, turning the transistor on while the voltage source is disconnected from the capacitor, measuring a voltage signal across the resistor while the transistor is turned on, and determining a test result indicating whether the transistor has an acceptable dynamic on-state resistance according to the voltage signal across the resistor.