A testing circuit includes a first circuit and a second circuit. The first circuit has a first capacitor and a second capacitor. The first circuit is configured to transfer at least a portion of a first voltage across the first capacitor to the second capacitor. The second circuit has the first capacitor and the second capacitor. The second circuit is configured to transfer at least a portion of a second voltage across the second capacitor to the first capacitor.

A method of testing a semiconductor device, in a package, having a junction between a semiconductor material of a first type and a semiconductor material of a second type. The junction has a temperature dependent breakdown voltage, and the method includes the steps of determining the breakdown voltage, providing a fixed voltage over the junction, via pins of the package, and the fixed voltage is higher than the breakdown voltage, and measuring, via pins of the package, a breakdown current flowing through the junction, determining a dissipated power based on the fixed voltage and the measured breakdown current, and the dissipated power is a qualitive measure for the semiconductor device.

A system includes a controller that is configured to generate a plurality of switch control signals; a plurality of electrical circuit elements, the plurality of electrical circuit elements being characterized by a plurality of impedances, respectively; a plurality of voltage sources; and a plurality of switches that are programmable to couple the plurality of electrical circuit elements to the plurality of voltage sources responsive to the plurality of switch control signals.

A test system, a method for manufacturing an electronic device, and a method for testing a wafer or electronic device that includes coupling a transistor in a series circuit with a capacitor and a resistor, coupling a voltage source to the capacitor to charge the capacitor to a non-zero DC voltage while the transistor is turned off, disconnecting the voltage source from the capacitor while the transistor is turned off, turning the transistor on while the voltage source is disconnected from the capacitor, measuring a voltage signal across the resistor while the transistor is turned on, and determining a test result indicating whether the transistor has an acceptable dynamic on-state resistance according to the voltage signal across the resistor.

Test structures for a body-contacted field effect transistor (BCFET) include: a single-pad structure with body contact and probe pad regions connected to a channel region at first and second connection points with a known separation distance between the connection points; and a multi-pad structure with a body contact region connected to a channel region at a first connection point and multiple probe pad regions connected to the channel region at second connection points that are separated from the first connection point by different separation distances. A method includes: determining separation distance-dependent internal body potentials at the second connection points in response to different bias conditions by using either multiple single-pad structures, each having a different separation distance between the connection points, or by using a multi-pad structure; and based on the separation distance-dependent internal body potentials, generating a model representing the BCFET with body-contacted and floating body devices.

The disclosed technology relates generally to semiconductor devices, and more particularly to semiconductor devices including a metal-oxide-semiconductor (MOS) transistor and are configured for accelerating and monitoring degradation of the gate dielectric of the MOS transistor. In one aspect, a semiconductor device configured with gate dielectric monitoring capability comprises a metal-oxide-semiconductor (MOS) transistor including a source, a drain, a gate, and a backgate region formed in a semiconductor substrate. The semiconductor device additionally comprises a bipolar junction transistor (BJT) including a collector, a base, and an emitter formed in the semiconductor substrate, wherein the backgate region of the MOS transistor serves as the base of the BJT and is independently accessible for activating the BJT. The MOS transistor and the BJT are configured to be concurrently activated by biasing the backgate region independently from the source of the MOS transistor, such that the base of the BJT injects carriers of a first charge type into the backgate region of the MOS transistor, where the first charge type is opposite charge type to channel current carriers.

A semiconductor apparatus includes: a device having a terminal; and a protection circuit configured to be connected to the terminal of the device, the protection circuit including at least two unidirectional conduction circuits connected in anti-parallel, the two unidirectional conduction circuits configured to have current directions opposite to each other in an on state, wherein the protection circuit is so configured that, at least one of the two unidirectional conduction circuits is turned on to release charges accumulated at the terminal when a voltage at the terminal of the device is out of a predetermined protection voltage range

An example semiconductor wafer includes a semiconductor layer, a dielectric layer disposed on the semiconductor layer, and a layer of the metal disposed on the dielectric layer. An example method of determining an effective work function of a metal on the semiconductor wafer includes determining a surface barrier voltage of the semiconductor wafer, and determining a metal effective work function of the semiconductor wafer based, at least in part, on the surface barrier voltage.

An integrated circuit includes a semiconductor die having conductive pads and an electronic component with a first terminal coupled to a third conductive pad and a second terminal coupled to a fourth conductive pad. A resistor has a first terminal coupled to the fourth conductive pad and a second terminal coupled to the fifth conductive pad, and a first transistor has a first terminal coupled to the first conductive pad, a second terminal coupled to the fifth conductive pad, and a control terminal. A second transistor has a first terminal coupled to the first transistor, a second terminal coupled to the third conductive pad, and a control terminal. A pulse generator has an input coupled to the second conductive pad and an output coupled to the control terminal of the second transistor.

Provided are a charge trap evaluation method and semiconductor device including, in an embodiment, a step for applying an initialization voltage that has the same sign as a threshold voltage and is greater than or equal to the threshold voltage between the source electrode 15 and drain electrode 16 of a semiconductor device 1 having an HEMT structure and the substrate 10 of the semiconductor device 1 and initializing a trap state by forcing out trapped charge from a trap level and a step for monitoring the current flowing between the source electrode 15 and drain electrode 16 after the trap state initialization and evaluating at least one from among charge trapping, current collapse, and charge release.