The present invention concerns a method and a device for increasing the reliability of a power module composed of plural power semiconductors that are connected in parallel, the power semiconductors being connected to the external pins of the package of the power module through metallic connections. The invention - selects one power semiconductor among the power semiconductors connected in parallel according to a criterion. - applies a same input patient to the not selected power semiconductors connected in parallel. - increases the temperature of the selected power semiconductor in order to reach a target temperature of tlic power semicon- ductor dunng a time duration m order to achieve and interface grain homogenisation of the metallic connections of tlic selected power semiconductor. - applies the same input pattern to tlic selected pow er semiconductor after tlic time duration.

A diagnostic system for a DC-DC voltage converter is provided. The diagnostic system includes a first temperature sensor generating a first output voltage indicating a temperature level of a high voltage bi-directional MOSFET switch. The diagnostic system includes a microcontroller that samples the first output voltage at a first sampling rate utilizing a first channel in a first bank of channels to obtain a first predetermined number of voltage samples. The microcontroller determines a first number of voltage samples in the first predetermined number of voltage samples in which the first output voltage is greater than a first threshold voltage. The microcontroller sets a first temperature diagnostic flag equal to a first fault value if the first number of voltage samples is greater than a first threshold number of voltage samples indicating the high voltage bi-directional MOSFET switch has an over-temperature condition.

An object is to provide a semiconductor device capable of accurately detecting a temperature of a transistor part and a temperature of the diode part, and improving an overheat protection function. A semiconductor device includes a semiconductor chip having a cell region made up of a plurality of cells including cells corresponding to a transistor part and a diode part, respectively, a temperature detection part detecting a temperature of the transistor part, and a temperature detection part detecting a temperature of the diode part, the temperature detection part is disposed in the cell corresponding to the transistor part, and the temperature detection part is disposed in the cell corresponding to the diode part.

The present disclosure provides techniques for predicting failure of power switches and taking action based on the predictions. In an example, a method can include controlling the at least two parallel-connected power switches via a first driver and a second driver, the first a second driver responsive to a single command signal, measuring a failure characteristic of a first power switch, and disabling a first driver of the first power switch when the first failure characteristic exceeds a failure precursor threshold.

A method analyzes an operation of a power semiconductor device. The method includes: providing a set of reference voltages of the power semiconductor device and a set of corresponding reference currents; measuring an on-state voltage and a corresponding on-state current of the power semiconductor device to obtain a measurement point; adapting the set of reference voltages by adapting two of the set of reference voltages lying closest to the measurement point by extrapolating the measurement point; and using the adapted set of reference voltages to analyze the operation of the power semiconductor device. The extrapolation is based on a predefined reference increment current and a predefined reference increment voltage.

A system can include a plurality of device under test (DUT) cells. Each DUT cell can include a DUT and a plurality of switches configured to control a flow of current to the DUT. The system can further include a controller configured to execute a plurality of test to the plurality of DUTs in the plurality of DUT cells. Each of the plurality of tests comprises applying a measurement condition to a given DUT of the plurality of DUTs and concurrently applying a stress condition to the remaining DUTs of the plurality of DUTs, wherein the plurality of tests can provide measurements sufficient to determine a bias thermal instability and a time dependent dielectric breakdown of the given DUT.

A method analyzes an operating condition of a power converter. The method includes: providing a sample clock signal; determining repeatedly at least one operating parameter of a power semiconductor device of the power converter; and determining the operating condition of the power converter depending on the at least one determined operating parameter. The repetitions of the determining the at least one operating parameter are synchronous to the sample clock signal. For a given repetition of the determination of the at least one operating parameter, determining the at least one operating parameter includes measuring the at least one operating parameter or identifying a value for the at least one operating parameter from a previous repetition depending on a switching behavior of the power converter within the given repetition.

A semiconductor die includes: a SiC substrate; power and current sense transistors integrated in the substrate such that the current sense transistor mirrors current flow in the main power transistor; a gate terminal electrically connected to gate electrodes of both transistors; a drain terminal electrically connected to a drain region in the substrate and which is common to both transistors; a source terminal electrically connected to source and body regions of the power transistor; a dual mode sense terminal; and a doped resistor region in the substrate between the transistors. The dual mode sense terminal is electrically connected to source and body regions of the current sense transistor. The doped resistor region has a same conductivity type as the body regions of both transistors and is configured as a temperature sense resistor that electrically connects the source terminal to the dual mode sense terminal.

A circuit is powered through a transistor whose thermal instability behavior is to be evaluated in a stress test. The transistor is stressed during a stress phase of the stress test with a sensor circuit powered off and the Vds of the transistor is zero. The sensor circuit is powered on through the transistor during an evaluate phase of the stress test.

A test apparatus includes a tray including at least a first region and a second region, and a cap disposed over the tray. The cap includes a cap body, and at least a first magnet and a second magnet disposed over the cap body. The first magnet is configured to provide a first magnetic field to the first region of the tray, and the second magnet is configured to provide a second magnetic field to the second region of the tray. A strength of the first magnetic field is different from a strength of the second magnetic field.