According to one embodiment, an electronic circuit includes: a current supply circuit, a detection circuit, a timing generation circuit, a sample hold circuit and a calculation circuit. The current supply circuit supplies a sine wave current for measurement to a gate terminal of a semiconductor switching device. The detection circuit detects a sine wave voltage generated in response to supply of the sine wave current to generate a detection signal. The timing generation circuit counts cycles of the sine wave voltage. The sample hold circuit samples the detection signal at a timing depending on a count value of the timing generation circuit. The calculation circuit calculates a gate resistance of the semiconductor switching device based on the sampled voltage.

The present disclosure relates to a monitoring system for a plurality of power devices serially connected in a main circuit of a current transmission path comprising a first power device and a second power device each including a semiconductor element; a first sensor connected to the first and second power devices, and which senses information related to a first current flowing in the first power device; a second sensor for sensing information related to a second current flowing in the second power device; a third sensor for sensing information related to a third current flowing between the first power device and the second power device; and a control unit for comparing the first current and the second current on the basis of the third current measured by the third sensor, and determining whether the state of each power device is abnormal based on a difference with the third current.

A physical property of a test sample with a conductive or semi-conductive material (line/area/volume) is obtained. Periodic Joule heating is induced within the test sample by passing an AC current across a first pair of probe terminals electrically connected to the test sample, measuring the voltage drop across a second pair of probe terminals electrically connected to the test sample at one and three times the fundamental excitation frequency of the current-conducting terminals, and calculating the temperature-modulated property/properties of the test sample as a function of the potential drop measurement(s). This includes: a) determining a value proportional to the TCR of the test sample, b) a geometric parameter of the test sample (affected by coupling of its TCR to heat transport to/from the test sample), or c) the true resistivity of the test sample at the ambient experimental temperature by subtracting measurable and accountable TCR offset(s).

A method analyzes an operating condition of a power converter. The method includes: providing a sample clock signal; determining repeatedly at least one operating parameter of a power semiconductor device of the power converter; and determining the operating condition of the power converter depending on the at least one determined operating parameter. The repetitions of the determining the at least one operating parameter are synchronous to the sample clock signal. For a given repetition of the determination of the at least one operating parameter, determining the at least one operating parameter includes measuring the at least one operating parameter or identifying a value for the at least one operating parameter from a previous repetition depending on a switching behavior of the power converter within the given repetition.

A method for assessing the state of damage of a semiconductor module that is subject to operational loading, in particular a semiconductor module of a drive system converter, that includes at least one semiconductor component arranged on or in a support structure. It is possible not only to estimate a spent service life for the entire semiconductor module, but also to detect unexpected or undesirable loading states and thus a premature reduction of the remaining service life of the semiconductor module. Continuous load assessments are thus possible already during the operation of the semiconductor module and allow interventions to be made in good time.

A test method and device for a contact resistor are provided, configured to test a contact resistor of a metal-oxide-semiconductor (MOS) transistor. The method includes: a resistance value per area and a temperature coefficient of resistance of the contact resistor are acquired; and a target resistance value of the contact resistor is determined according to the resistance value per area, the temperature coefficient of resistance, and an area of the contact resistor.

The disclosure relates to technology for determining stress on integrated circuits. These include using ring oscillators formed on the integrated circuit, where one ring oscillator has its frequency dependent on the current flowing through its stages being limited by its NMOS devices and another ring oscillator has its frequency dependent on the current flowing through its stages being limited by its PMOS devices. This allows the stress on the integrated circuit to be determined in different directions along the integrated circuit. A temperature sensor can be used to compensate for temperature dependence on the frequencies of the ring oscillators.

A method for determining a thermal impedance of a sample device is described. According to the method, a sample device is heated to an initial temperature. A pulsed power including a sequence of pulses is applied to the sample device. Temperature of the sample device is measured in a time-dependent manner. A thermal impedance of the sample device is determined based on the temperature of the sample device and the pulsed power.

A test method and device for a contact resistor are provided, configured to test a contact resistor of a metal-oxide-semiconductor (MOS) transistor. The method includes: a resistance value per area and a temperature coefficient of resistance of the contact resistor are acquired; and a target resistance value of the contact resistor is determined according to the resistance value per area, the temperature coefficient of resistance, and an area of the contact resistor.

A semiconductor die includes: a SiC substrate; power and current sense transistors integrated in the substrate such that the current sense transistor mirrors current flow in the main power transistor; a gate terminal electrically connected to gate electrodes of both transistors; a drain terminal electrically connected to a drain region in the substrate and which is common to both transistors; a source terminal electrically connected to source and body regions of the power transistor; a dual mode sense terminal; and a doped resistor region in the substrate between the transistors. The dual mode sense terminal is electrically connected to source and body regions of the current sense transistor. The doped resistor region has a same conductivity type as the body regions of both transistors and is configured as a temperature sense resistor that electrically connects the source terminal to the dual mode sense terminal.