Disclosed examples include systems to determine an on-state impedance of a high voltage transistor, and measurement circuits to measure the drain voltage of a drain terminal of the high voltage transistor during switching, including an attenuator circuit to generate an attenuator output signal representing a voltage across the high voltage transistor when the high voltage transistor is turned on, and a differential amplifier to provide an amplified sense voltage signal according to the attenuator output signal. The attenuator circuit includes a clamp transistor coupled with the drain terminal of the high voltage transistor to provide a sense signal to a first internal node, a resistive voltage divider circuit to provide the attenuator output signal based on the sense signal, and a first clamp circuit to limit the sense signal voltage when the high voltage transistor is turned off.

Systems and methods are described herein for charge-based capacitor measurement. The system includes a first pseudo-inverter circuit and a second pseudo-inverter circuit. The system also includes a control circuit coupled between the first inverter circuit and the second inverter circuit. The control circuit is configured to generate independent and non-overlapping control signals for the first pseudo-inverter circuit and the second pseudo-inverter circuit. A shielding metal is coupled to the first pseudo-inverter circuit, the second pseudo-inverter circuit, and the control circuit. The shielding metal is configured to dissipate parasitic capacitance of at least one of the first pseudo-inverter circuit or the second pseudo-inverter circuit. A device under test is coupled to each of the first inverter circuit and the second inverter circuit.

An electronic test equipment apparatus includes a power terminal configured to receive power, an interface for a device under test (DUT), at least one power transistor connected in series between the power terminal and the interface for the DUT, and a protection circuit. The protection circuit is configured to: switch on the at least one power transistor, to electrically connect the power terminal to the DUT through the interface as part of a test routine; and subsequently automatically switch off the at least one power transistor after a predetermined delay, to electrically disconnect the power terminal from the DUT regardless of whether the DUT passes or fails the test routine. A voltage clamp circuit for electronic test equipment and corresponding methods of testing devices using such electronic test equipment are also described.

Techniques for isolating interfaces while testing a semiconductor device include a semiconductor device having a link interface that couples the semiconductor device to a high-speed data transfer link, a clock control unit that transmits one or more clock signals to the link interface; and a protection module. The protection module asserts a clock stop request to the clock control unit and, in response to receiving a clock stop acknowledgement from the clock control unit, asserts a clamp enable to cause the link interface to be isolated from portions of the semiconductor device. After waiting for a first predetermined period of time to expire, the protection module de-asserts the clock stop request.

A test and measurement instrument has a user interface, one or more probes to allow the instrument to connect to a device under test (DUT), and one or more processors configured to execute code to cause the one or more processors to: receive one or more user inputs through the user interface, at least one of the user inputs to identify at least one analysis to be performed on the DUT, receive waveform data from the DUT when the DUT is activated by application of power from a power supply, and application of one of a first and second pulse or multiple pulses from a source instrument, perform the at least one analysis on the waveform data, and display the waveform data and analysis on the user interface. A method of automatically performing a double pulse test and analysis on a device under test (DUT) includes receiving a user input through a user interface on a test and measurement instrument, the user input to identify at least one analysis to be performed on waveform data received from the DUT, receiving the waveform data from the DUT when the DUT is activated by application of power from a power supply, and application of one of a first and a second pulse or multiple pulses from a source instrument, performing the analysis on the waveform data, and displaying the waveform data and analysis on the user interface.

A test and measurement instrument has a user interface, one or more probes to connect to a device under test (DUT), and one or more processors configured to execute code to cause the one or more processors to: receive waveform data from the DUT after activation of the DUT by application of power from a power supply, and application of at least a first and second pulse from a source instrument, locate one or more reverse recovery regions in the waveform data, determine a reverse recovery time for the DUT from the reverse recovery region, and display a reverse recovery plot of the one or more reverse recovery regions on the user interface, the reverse recovery plot being automatically configured to display one or more of the reverse recovery regions, and including at least one characteristic for the one or more reverser recovery regions annotated on the reverse recovery plot. A method of providing reverse recovery measurements for a device under test (DUT) includes receiving waveform data through the probes from the DUT after activation of the DUT by application of power from a power supply, and application of a first and second pulse from a source instrument, locating one or more reverse recovery regions in the waveform data, determining a reverse recovery time for the DUT for the one or more reverse recovery regions, and displaying a reverse recovery plot of the one or more reverse recovery regions on the user interface, the reverse recovery plot being automatically configured to display the one or more reverse recovery regions, and including at least one characteristic of the one or more reverse recovery regions annotated on the reverse recovery plot.

A method for fabricating a MOMCAP includes steps as follows: An Nth metal layer is formed on a substrate according to an Nth expected capacitance value of the Nth metal layer. An Nth capacitance error value between an Nth actual capacitance value of the Nth metal layer and the Nth expected capacitance value is calculated. An N+1th expected capacitance value of an N+1th metal layer is adjusted to form an N+1th actual capacitance value according to the Nth capacitance error value, and the N+1th metal layer with an N+1th actual capacitance value is formed on the Nth metal layer according to the adjusted N+1th expected capacitance value, to make the sum of the Nth actual capacitance value and the N+1th actual capacitance value equal to the sum of the Nth expected capacitance value and the N+1th expected capacitance value. N is an integer greater than 1.

Circuitry for testing an integrated capacitor that includes a first capacitor, a supply node for connecting to a voltage supply, a test node for connecting to the integrated capacitor, and a charge monitoring circuit. The circuitry is operable in a sequence of states including a first state in which the first capacitor is connected to the supply node and is disconnected from the test node so as to charge the first capacitor to a test voltage and a second state in which the first capacitor is disconnected from the supply node and is connected to the test node to apply the test voltage to the integrated capacitor. The charge monitoring circuit is configured to monitor a charge transfer from the first capacitor to the integrated capacitor in said second state and to generate a measurement value based on an amount of the charge transfer.

This document discloses a power leakage sensor for a circuit, comprising: a power switch controller circuit coupled with at least one power switch for the digital circuit, the power switch controller configured to control the at least one power switch, to monitor power supply of the digital circuit, and to perform the following: a. in response to the detecting that the power supply to the circuit is powered on, output a power-off signal to the at least one power switch; and b. in response to the measured power supply metric falling below a threshold in response to the power-off signal, output a power-on signal to the at least one power switch. The power leakage sensor further comprises a frequency counter circuit configured to count a frequency of executing steps a. and b., the frequency indicating a proportion of power leakage in the digital circuit.

Systems, devices, and methods for characterizing semiconductor devices and thin film materials. The device consists of multiple probe tips that are integrated on a single substrate. The layout of the probe tips could be designed to match specific patterns on a CMOS chip or sample. The device provides for detailed studies of transport mechanisms in thin film materials and semiconductor devices.