Circuitry for testing an integrated capacitor that includes a first capacitor, a supply node for connecting to a voltage supply, a test node for connecting to the integrated capacitor, and a charge monitoring circuit. The circuitry is operable in a sequence of states including a first state in which the first capacitor is connected to the supply node and is disconnected from the test node so as to charge the first capacitor to a test voltage and a second state in which the first capacitor is disconnected from the supply node and is connected to the test node to apply the test voltage to the integrated capacitor. The charge monitoring circuit is configured to monitor a charge transfer from the first capacitor to the integrated capacitor in said second state and to generate a measurement value based on an amount of the charge transfer.

Systems, devices, and methods for characterizing semiconductor devices and thin film materials. The device consists of multiple probe tips that are integrated on a single substrate. The layout of the probe tips could be designed to match specific patterns on a CMOS chip or sample. The device provides for detailed studies of transport mechanisms in thin film materials and semiconductor devices.

An electronic test equipment apparatus includes a power terminal configured to receive power, an interface for a device under test (DUT), at least one power transistor connected in series between the power terminal and the interface for the DUT, and a protection circuit. The protection circuit is configured to: switch on the at least one power transistor, to electrically connect the power terminal to the DUT through the interface as part of a test routine; and subsequently automatically switch off the at least one power transistor after a predetermined delay, to electrically disconnect the power terminal from the DUT regardless of whether the DUT passes or fails the test routine. A voltage clamp circuit for electronic test equipment and corresponding methods of testing devices using such electronic test equipment are also described.

Systems, devices, and methods for characterizing semiconductor devices and thin film materials. The device consists of multiple probe tips that are integrated on a single substrate. The layout of the probe tips could be designed to match specific patterns on a CMOS chip or sample. The device provides for detailed studies of transport mechanisms in thin film materials and semiconductor devices.

Techniques for isolating interfaces while testing a semiconductor device include a semiconductor device having a link interface that couples the semiconductor device to a high-speed data transfer link, a clock control unit that transmits one or more clock signals to the link interface; and a protection module. The protection module asserts a clock stop request to the clock control unit and, in response to receiving a clock stop acknowledgement from the clock control unit, asserts a clamp enable to cause the link interface to be isolated from portions of the semiconductor device. After waiting for a first predetermined period of time to expire, the protection module de-asserts the clock stop request.

An operational amplifier circuit includes a potential control circuit connected between a current sense semiconductor element connected in parallel with a main semiconductor element and a current detection resistor. The potential control circuit controls an output potential of the current sense semiconductor element to be equal to that of the main semiconductor element. The potential control circuit includes a current control element controlling an output current of the current sense semiconductor element and an operational amplifier outputting a signal corresponding to an output potential difference between the current sense semiconductor element and the main semiconductor element to the current control element. An input offset voltage polarity determination unit determines a polarity of an input offset voltage of the operational amplifier according to the output potential difference. The polarity of the input offset voltage is controlled to be constant based on polarity determination of the input offset voltage.

A method for predicting remaining life of electromigration failure is disclosed. The methods includes: establishing an electromigration life model of a MOS device; acquiring a normal electromigration failure lifetime .sub.1, based on a current density and a first environment temperature under a preset normal operating condition and the electromigration life model; acquiring a current density stress, based on a target prognostic point .sub.2, a second environment temperature and the electromigration life model; inputting the current density stress into a MOS device electromigration failure warning circuit based on a prognostic cell; and if the prognostic circuit of EM failure for a MOS device outputs a high level after a time .sub.3, acquiring a remaining life of electromigration failure corresponding to .sub.2 based on .sub.1, .sub.2 and .sub.3. A device for remaining life prediction for electromigration failure is also disclosed.

With a conventional high-frequency measurement method, it is difficult to accurately grasp variation in high-frequency performance when a high-frequency signal is input to an amplifier. One aspect of a high-frequency measurement method according to the present invention includes generating a test signal (TS), which is a sine-wave signal having a predetermined frequency, in which a period () during which the power level is at a first power level and a period (T-) during which the power level is at a second power level lower than the first power level are periodically repeated, inputting the test signal (TS) to a device under test (10) as an input signal, and measuring the difference between an output signal (OUT) of the device under test (10) and an ideal value of the output signal (OUT).

In a method for obtaining the equivalent oxide thickness of a dielectric layer, a first semiconductor capacitor including a first silicon dioxide layer and a second semiconductor capacitor including a second silicon dioxide layer are provided and a modulation voltage is applied to the semiconductor capacitors to measure a first scanning capacitance microscopic signal and a second scanning capacitance microscopic signal. According to the equivalent oxide thicknesses of the silicon dioxide layers and the scanning capacitance microscopic signals, an impedance ratio is calculated. The modulation voltage is applied to a third semiconductor capacitor including a dielectric layer to measure a third scanning capacitance microscopic signal. Finally, the equivalent oxide thickness of the dielectric layer is obtained according to the equivalent oxide thickness of the first silicon dioxide layer, the first scanning capacitance microscopic signal, third scanning capacitance microscopic signal, and the impedance ratio.

An operational amplifier circuit includes a potential control circuit connected between a current sense semiconductor element connected in parallel with a main semiconductor element and a current detection resistor. The potential control circuit controls an output potential of the current sense semiconductor element to be equal to that of the main semiconductor element. The potential control circuit includes a current control element controlling an output current of the current sense semiconductor element and an operational amplifier outputting a signal corresponding to an output potential difference between the current sense semiconductor element and the main semiconductor element to the current control element. An input offset voltage polarity determination unit determines a polarity of an input offset voltage of the operational amplifier according to the output potential difference. The polarity of the input offset voltage is controlled to be constant based on polarity determination of the input offset voltage.