A method for MOM capacitance value control is disclosed. The method comprises: S01: setting a target thicknesses for each metal layers; S02: after forming a current metal layer, measuring a thickness of the current metal layer; when the thickness of the current metal layer is equal to or less than a threshold value, then turning to step S03; S03: calculating multiple capacitance variations related to the current metal layer according to the thickness of the current metal layer; wherein each of the capacitance variation related to the current metal layer is between an actual capacitance value of a MOM capacitor combination associated with the current metal layer and a target capacitance value of the same MOM capacitor combination; S04: calculating updated target thicknesses for all subsequent metal layers according to the capacitance variations related to the current metal layer.

Disclosed examples include systems to determine an on-state impedance of a high voltage transistor, and measurement circuits to measure the drain voltage of a drain terminal of the high voltage transistor during switching, including an attenuator circuit to generate an attenuator output signal representing a voltage across the high voltage transistor when the high voltage transistor is turned on, and a differential amplifier to provide an amplified sense voltage signal according to the attenuator output signal. The attenuator circuit includes a clamp transistor coupled with the drain terminal of the high voltage transistor to provide a sense signal to a first internal node, a resistive voltage divider circuit to provide the attenuator output signal based on the sense signal, and a first clamp circuit to limit the sense signal voltage when the high voltage transistor is turned off.

In a method for obtaining the equivalent oxide thickness of a dielectric layer, a first semiconductor capacitor including a first silicon dioxide layer and a second semiconductor capacitor including a second silicon dioxide layer are provided and a modulation voltage is applied to the semiconductor capacitors to measure a first scanning capacitance microscopic signal and a second scanning capacitance microscopic signal. According to the equivalent oxide thicknesses of the silicon dioxide layers and the scanning capacitance microscopic signals, an impedance ratio is calculated. The modulation voltage is applied to a third semiconductor capacitor including a dielectric layer to measure a third scanning capacitance microscopic signal. Finally, the equivalent oxide thickness of the dielectric layer is obtained according to the equivalent oxide thickness of the first silicon dioxide layer, the first scanning capacitance microscopic signal, third scanning capacitance microscopic signal, and the impedance ratio.

This document discloses a power leakage sensor for a circuit, comprising: a power switch controller circuit coupled with at least one power switch for the digital circuit, the power switch controller configured to control the at least one power switch, to monitor power supply of the digital circuit, and to perform the following: a. in response to the detecting that the power supply to the circuit is powered on, output a power-off signal to the at least one power switch; and b. in response to the measured power supply metric falling below a threshold in response to the power-off signal, output a power-on signal to the at least one power switch. The power leakage sensor further comprises a frequency counter circuit configured to count a frequency of executing steps a. and b., the frequency indicating a proportion of power leakage in the digital circuit.

Systems and methods are described herein for charge-based capacitor measurement. The system includes a first pseudo-inverter circuit and a second pseudo-inverter circuit. The system also includes a control circuit coupled between the first inverter circuit and the second inverter circuit. The control circuit is configured to generate independent and non-overlapping control signals for the first pseudo-inverter circuit and the second pseudo-inverter circuit. A shielding metal is coupled to the first pseudo-inverter circuit, the second pseudo-inverter circuit, and the control circuit. The shielding metal is configured to dissipate parasitic capacitance of at least one of the first pseudo-inverter circuit or the second pseudo-inverter circuit. A device under test is coupled to each of the first inverter circuit and the second inverter circuit.

CMOS switching devices are connected to testing equipment that applies AC to stress the CMOS switching devices. The testing equipment varies rise and fall times of drain and gate voltages, and varies offsets of the drain and gate voltages of the CMOS switching devices. The amount of hot carrier injection (HCI) within the CMOS switching devices is measured when the rise and fall times of the drain and gate voltages cross over, to establish AC HCI contribution to device degradation of the CMOS switching devices. Further, these methods can correlate the AC HCI contribution of the CMOS switching devices to CMOS logic devices based on ring oscillator (RO) degradation of ROs similarly tested or simulated, to produce AC HCI contribution for the CMOS logic devices.

A method for MOM capacitance value control is disclosed. The method comprises: S01: setting a target thicknesses for each metal layers; S02: after forming a current metal layer, measuring a thickness of the current metal layer; when the thickness of the current metal layer is equal to or less than a threshold value, then turning to step S03; S03: calculating multiple capacitance variations related to the current metal layer according to the thickness of the current metal layer; wherein each of the capacitance variation related to the current metal layer is between an actual capacitance value of a MOM capacitor combination associated with the current metal layer and a target capacitance value of the same MOM capacitor combination; S04: calculating updated target thicknesses for all subsequent metal layers according to the capacitance variations related to the current metal layer.

Disclosed examples include systems to determine an on-state impedance of a high voltage transistor, and measurement circuits to measure the drain voltage of a drain terminal of the high voltage transistor during switching, including an attenuator circuit to generate an attenuator output signal representing a voltage across the high voltage transistor when the high voltage transistor is turned on, and a differential amplifier to provide an amplified sense voltage signal according to the attenuator output signal. The attenuator circuit includes a clamp transistor coupled with the drain terminal of the high voltage transistor to provide a sense signal to a first internal node, a resistive voltage divider circuit to provide the attenuator output signal based on the sense signal, and a first clamp circuit to limit the sense signal voltage when the high voltage transistor is turned off.

A method for predicting remaining life of electromigration failure is disclosed. The methods includes: establishing an electromigration life model of a MOS device; acquiring a normal electromigration failure lifetime .sub.1, based on a current density and a first environment temperature under a preset normal operating condition and the electromigration life model; acquiring a current density stress, based on a target prognostic point .sub.2, a second environment temperature and the electromigration life model; inputting the current density stress into a MOS device electromigration failure warning circuit based on a prognostic cell; and if the prognostic circuit of EM failure for a MOS device outputs a high level after a time .sub.3, acquiring a remaining life of electromigration failure corresponding to .sub.2 based on .sub.1, .sub.2 and .sub.3. A device for remaining life prediction for electromigration failure is also disclosed.

Systems and methods are described herein for charge-based capacitor measurement. The system includes a first pseudo-inverter circuit and a second pseudo-inverter circuit. The system also includes a control circuit coupled between the first inverter circuit and the second inverter circuit. The control circuit is configured to generate independent and non-overlapping control signals for the first pseudo-inverter circuit and the second pseudo-inverter circuit. A shielding metal is coupled to the first pseudo-inverter circuit, the second pseudo-inverter circuit, and the control circuit. The shielding metal is configured to dissipate parasitic capacitance of at least one of the first pseudo-inverter circuit or the second pseudo-inverter circuit. A device under test is coupled to each of the first inverter circuit and the second inverter circuit.