A method for assessing a thermal path associated with an integrated circuit includes identifying a heat application mode based on a design type of the integrated circuit. The method also includes measuring a first temperature of at least one thermal sensing device associated with the integrated circuit. The method also includes applying heat to at least a portion of the integrated circuit according to the heat application mode. The method also includes measuring a second temperature of the at least one thermal sensing device. The method also includes determining a difference between the first temperature and the second temperature. The method also includes determining whether a thermal path between the integrated circuit and an associated substrate is sufficient based on a comparison of the difference between the first temperature and the second temperature with a predetermined difference between an initial temperature and a subsequent temperature of the at least one thermal sensing device.

A method of testing an integrated circuit die (IC) for cracks includes performing an assembly process on a wafer including multiple ICs including: lowering a tip of a first manipulator arm to contact and pick up a given IC, flipping the given IC such that a surface of the IC facing the wafer faces a different direction, and transferring the IC to a tip of a second manipulator arm, applying pressure from the second manipulator arm to the given IC such that pogo pins extending from the tip of the first manipulator arm make electrical contact with conductive areas of the IC for connection to a crack detector on the IC, and performing a conductivity test on the crack detector using the pogo pins. If the conductivity test indicates a lack of presence of a crack, then the second manipulator arm is used to continue processing of the given IC.

There is provided an aircraft engine printed circuit board assembly generally having a functional circuit contributing to the operation of an aircraft engine. The functional circuit has a first substrate portion, a first electronic component supported by the first substrate portion, and a first electrical conductor supported by the first substrate portion and leading to the first electronic component. The aircraft engine printed circuit board assembly generally has a monitoring circuit having a second substrate portion, a second electronic component supported by the second substrate portion, a second electrical conductor supported by the second substrate portion and leading to the second electronic component, the second electrical conductor having a shorter life expectancy than the first electrical conductor, and a detector monitoring an indicator of operativeness of the second electrical conductor, in which the first electrical conductor and the second electrical conductor are both exposed to the same environment.

A first input unit receives an analog signal from a pair of input terminals, to which a sensor is connected, as a differential input via a pair of first input lines between which a first resistor is interposed. The analog signal input device converts the analog signals read via the first input unit and a second input unit having a similar configuration into a multi-bit digital signal and outputs the digital signal. When a prescribed instruction is received, a current is supplied from one of the pair of first input lines to a power supply line, and it is determined that there an open circuit when the output of the second input unit obtained when the output of the first input unit has increased in response to the current supply from the current supply unit is equal to or larger than a predetermined threshold value.

An apparatus is provided for testing a PCIe interface on a printed circuit assembly. The apparatus can include a plurality of electrical contacts to couple to a PCIe interface of the printed circuit assembly, wherein a respective electrical contact corresponds to a pin of the PCIe interface. The apparatus can also include a plurality of resistors. Each resistor is coupled between two adjacent electrical contacts. At least one electrical contact corresponds to a ground, power, or not connected (NC) pin of the PCIe interface, thereby allowing a loopback test to determine connectivity between the pins of the PCIe interface and the printed circuit assembly.

Provided is a test device for roll-to-roll board of flexible circuit boards. The test device comprises a detection probe frame, front and rear ends of the detection probe frame being connected to a sliding frame, and a bottom of the sliding frame being connected to a magnetic plate; wherein the magnetic plate is consisted of a square panel in the middle and four isosceles trapezoidal panels in upright direction; the four isosceles trapezoidal panels is movable and is capable of being rotated towards the square panel; a bottom of the square panel is provided with 4×4 centralized ports, the angle between the centralized port and a vertical line of the panel is 30°; the upper surface of the magnetic plate is provided with four catching splints, the catching splint is movable on the magnetic plate.

A method for estimating degradation of a wire-bonded power semi-conductor module is provided. The method includes obtaining an indicator of degradation (Degr.sub.est_t-1); estimating an estimated indicator of degradation (Degr.sub.est_t) by a temporal degradation model; obtaining a set of on-line measure (X.sub.on_meas_t); then, (1) converting the on-line measure (X.sub.on_meas_t) into a deducted indicator of degradation (Degr.sub.meas_t) by an electrical equivalence model, and (2) computing a deviation between estimated and deducted indicator of degradation (Degr.sub.est_t; Degr.sub.meas_t); and/or (1) converting the estimated indicator of degradation (Degr.sub.est_t) into a set of on-line estimation (X.sub.on_est_t), and (2) computing a deviation between set of on-line measure and estimation (X.sub.on_meas_t; X.sub.on_est_t); and correcting the estimated indicator of degradation (Degr.sub.est_t) into a corrected estimated indicator of degradation (Degr.sub.corr_t) as a function of the computed deviation.

Methods of performing diagnostic tests on electroencephalography (EEG) recording devices comprising at least one stimulator coupled with a plurality of EEG electrode recording channels and corresponding recording channel connectors are performed by a test fixture comprising a plurality of resistors coupled with one or more of the EEG electrode recording channels and corresponding recording channel connectors. The methods include performing an impedance test for determining if each EEG recording channel of the EEG recording device has a predefined impedance, performing a channel uniqueness test for each EEG recording channel, performing a test for verifying the state of a switch of the stimulator of the EEG recording device, and performing a test for verifying connector IDs of the recording channel connectors connecting the EEG electrodes to respective EEG recording channels.

Various embodiments may provide systems and methods for determining a distance to a short in a two-conductor wire. Various embodiments may include determining a distance to a short in a two-conductor wire based at least in part on a phase difference between a phase of an injected tone and a phase of a reflected tone. Various embodiments may include determining a distance to a short in a two-conductor wire based at least in part on both a phase difference and an amplitude difference between an injected tone and a reflected tone. Various embodiments may include determining a distance to a short in a two-conductor wire based at least in part on a measured peak voltage of a combined pulse.

Methods of performing diagnostic tests on electroencephalography (EEG) recording devices comprising at least one stimulator coupled with a plurality of EEG electrode recording channels and corresponding recording channel connectors are performed by a test fixture comprising a plurality of resistors coupled with one or more of the EEG electrode recording channels and corresponding recording channel connectors. The methods include performing an impedance test for determining if each EEG recording channel of the EEG recording device has a predefined impedance, performing a channel uniqueness test for each EEG recording channel, performing a test for verifying the state of a switch of the stimulator of the EEG recording device, and performing a test for verifying connector IDs of the recording channel connectors connecting the EEG electrodes to respective EEG recording channels.