A dual printed circuit board assembly, a printed circuit board, and a modular printed circuit board are provided. The printed circuit board includes a plurality of first connection points. The modular printed circuit board includes a plurality of second connection points. The modular printed circuit board is adapted to be mounted on the printed circuit board and includes a sensing unit, a first detecting unit, and a first notifying unit. The sensing unit outputs a detecting voltage according to a contact state between the first connection points and the second connection points. The first detecting unit determines whether the first connection points are respectively connected to the corresponding second connection points according to the detecting voltage. When one of the first connection points is not connected to the corresponding one of the second connection points, the first detecting unit controls the first notifying unit to issue a notification.

A printed circuit arrangement employs a printed circuit board having a corrosion test circuit provided with at least two conductive pads which are located proximate to each other in a measuring area. The arrangement uses a measuring device to identify corrosion on other defects in the circuit board including short circuits and/or line cuts. One pad is an excitation pad, being connected to an excitation signal source, and the other pad is a response pad, whereby the measuring device is connected at least to the response pad.

An example apparatus includes a block configured to connect mechanically to a circuit board. The circuit board includes a first conductive path running to a first electrical contact on the circuit board and a second conductive path running to a second electrical contact on the circuit board. The first electrical contact and the second electrical contact are arranged in an area of the circuit board. The block includes a component having a surface that is configured to cover at least part of the area. A conductive layer is attached to at least part of the surface. The conductive layer is for creating a short circuit between the first electrical contact and the second electrical contact following connection of the block to the circuit board.

A motor controller circuit includes an electrical powertrain having a three phase input, a DC link and a three phase output, a controller including a processor and a memory, a first current sensor configured to sense a current at the three phase input, a second current sensor configured to sense a current at the three phase output, and a third sensor configured to sense a current at the DC link, and wherein the memory stores instructions configured to cause the processor to compare an operational model of the powertrain against a mathematical model of the powertrain and to detect a high impedance fault when a deviation between the operational model and the mathematical model exceeds a threshold.

A testing system includes a test machine, a plurality of probe sets, a data input device, a controller, a memory, and a data output device. The test machine has a platform for a DUT to be placed thereon, and a test arm which is movable relative to the platform. The probe sets are provided on the test machine with at least one probe set provided on the test arm to contact the DUT. The data input device is used to input information about the DUT. The controller is electrically connected to the test arm, the probe set on the test arm, and the data input device to move the test arm to a predetermined position according to the inputted information, and to make the probe set contact the DUT for electrical test. The memory saves electrical test result, which is outputted by the data output device.

A method for detecting a physical short-circuit defect between the first metal layer and a gate below. A first detection structure and a second detection structure are arranged in parallel in a detection region or a dicing channel region on a wafer, each detection structure comprises a P-type active detection, a detection gate structure, a contact hole in the P-type active detection, gate contact holes at two ends of the detection gate structure, a metal wire connected to the contact hole in the P-type active detection, and a metal wire connected to the gate contact hole. The detection gate structure of the first detection structure and the metal wire above it at least partially overlap. However, there is no projective overlap region between the detection gate structure of the second detection structure and the metal wire—above it.

Bridging testing method between adjacent semiconductor devices includes forming patterned diffusion region on semiconductor substrate, and forming first conductive layer over diffusion region. First conductive layer is patterned in same pattern as patterned diffusion region. Second conductive layer formed extending in first direction over first conductive layer. Second conductive layer is patterned to form opening extending in first direction in central region of second conductive layer exposing portion of first conductive layer. First conductive layer exposed portion is removed exposing portion of diffusion region. Source/drain region is formed over exposed portion of diffusion region, and dielectric layer is formed over source/drain region. Third conductive layer is formed over dielectric layer. End portions along first direction of second conductive layer removed to expose first and second end portions of first conductive layer. Electrical resistance across first conductive layer between first and second end portions of first conductive layer is measured.

An apparatus is provided for testing a PCIe interface on a printed circuit assembly. The apparatus can include a plurality of electrical contacts to couple to a PCIe interface of the printed circuit assembly, wherein a respective electrical contact corresponds to a pin of the PCIe interface. The apparatus can also include a plurality of resistors. Each resistor is coupled between two adjacent electrical contacts. At least one electrical contact corresponds to a ground, power, or not connected (NC) pin of the PCIe interface, thereby allowing a loopback test to determine connectivity between the pins of the PCIe interface and the printed circuit assembly.

A method of testing integrated circuit die for presence of a crack includes performing back end integrated circuit fabrication processes on a wafer having a plurality of integrated circuit die, the back end fabrication including an assembly process. The assembly process includes a) lowering a tip of a first manipulator arm to contact a given die such that pogo pins extending from the tip make electrical contact with conductive areas on the given die so that the pogo pins are electrically connected to a crack detector on the given die, b) picking up the given die using the first manipulator arm, and c) performing a conductivity test on the crack detector using the pogo pins to determine presence of a crack in the given die that extends from a periphery of the die, through a die seal ring of the die, and into an integrated circuit region of the die.

An apparatus configured to test an electrical system including one or more power supplies, a load, and one or more protective-isolation devices disposed between the one or more power supplies and the load is disclosed. The apparatus has a first measurement assembly configured to sense a first voltage or a first current at an input side of the one or more power supplies, a second measurement assembly configured to sense a second voltage or a second current at an output side of the one or more power supplies, and a third voltage or a third current between the one or more protective-isolation devices and the load, and a power controller electrically disposed between the second or third measurement assembly and a fault assembly. The fault assembly and the power controller are configured to selectively induce a fault, which is selected from a plurality of fault types, either to the output side of the electrical system or between the one or more protective-isolation devices and the load.