An apparatus for performing scan test of IC chip includes a shift-frequency searching unit that searches usable shift frequency for a target scan section among at least one scan section each including whole or part of at least one scan pattern inputted to a scan path. When searching usable shift frequency for the target scan section, the shift-frequency searching unit scales shift frequency of the target scan section differently from that of at least one scan section among scan sections shifted before or after the target scan section or sets shift frequency of the target scan section differently from that of the at least one scan section among the scan sections shifted before or after the target scan section, and searches shift frequency with which result of the scan test indicates pass or shift frequency with which result of the scan test indicates fail.

A computer implemented method, and an apparatus, are provided for performing a scalability check on a Hardware Description Language (HDL) representation of a circuit. The HDL representation identifies a plurality of sink signals, where each sink signal is arranged to take a result value computed by performing an operation using as input one or more driver signals. The method comprises creating within a storage a mapping table to map drivers signals to sink signals, where each entry identifies a sink signal and an associated sink width indication, identifies each driver signal used in the computation of the result value for that sink signal along with an associated driver width indication for each driver signal, and an operation type indication for the operation used to compute the result value for the sink signal. A scalability check operation is then executed on processing circuitry for one or more selected entries in the mapping table that have at least one of the sink and driver width indications specified with reference to at least one parameter. The scalability check operation comprises determining, using the operation type indication and the driver width indication for each driver signal, a driver signal identifying an expected width for the sink signal, and determining using the sink width indication a sink formula to identify the width of the sink signal. The sink formula and the driver formula are then evaluated to determine whether the presence of the at least one parameter gives rise to a scalability issue. A result file is then output identifying each sink signal that has been detected to have a scalability issue.

Generally discussed herein are systems, devices, and methods for determining if a circuit is acting improperly. A system can include a module to receive proper performance values of a circuit, a module to receive improper performance values of the circuit, a module to compare actual circuit input characteristics (X.sub.a) and actual circuit output characteristics (Y.sub.a) to X, Y, D, and Z to determine if the circuit is more likely operating properly or more likely operating improperly, and an alert module to, in response to determining the circuit is operating improperly, provide an alert to personnel indicating that the circuit is operating improperly or providing one or more signals to the circuit that cause the circuit to alter its current operation.

The present disclosure illustrates a testing circuit board with self-detection function and a self-detection method. A test for a to-be-tested circuit board is executed and a self-detection for a testing circuit board is performed by a JTAG chip. After the self-detection is passed, a first JTAG connection interface and a second JTAG connection interface are conducted by a controller, a multiplexer and a switch chip, to connect test circuit boards in series. Therefore, the efficiency of solving self-detection of JTAG chip with series connection conveniently and quickly may be achieved.

The system includes an integrated sequenced arrangement of parametric type instruments, automated guided prober test instruments, and a test instrument system using analog signature analysis for identifying faults in circuit card assemblies, under control of a software system with a mass interconnect system.

The disclosure describes a process and apparatus for accessing devices on a substrate. The substrate may include only full pin JTAG devices (504), only reduced pin JTAG devices (506), or a mixture of both full pin and reduced pin JTAG devices. The access is accomplished using a single interface (502) between the substrate (408) and a JTAG controller (404). The access interface may be a wired interface or a wireless interface and may be used for JTAG based device testing, debugging, programming, or other type of JTAG based operation.

An apparatus for performing a scan test of IC chip includes a shift-frequency searching unit that executes first scan test for first scan pattern whole or part of which constituting first scan section and second scan test for second scan pattern whole or part of which constituting second scan section, and searches usable shift frequency for the second scan section. The first scan pattern is scan pattern inputted to scan path right before the second scan pattern. The shift-frequency searching unit shifts the first scan section to the scan path with first shift frequency in the first scan test, shifts the second scan section to the scan path with second shift frequency in the second scan test, and determines, when both results of the first scan test and the second scan test indicate pass, the second shift frequency as the usable shift frequency for the second scan section.

A monitoring method is adapted for a circuit board. The circuit board includes a board body, a main circuit, and a standby circuit. The main circuit is located on the board body. The standby circuit is located on the board body, and is electrically connected to the main circuit. The standby circuit includes a first pressure detection circuit and a control circuit. The first pressure detection circuit is located at an area being monitored of the board body, and the control circuit outputs a first signal or a second signal according to a first detection value and a first predetermined range of the first pressure detection circuit.

Various embodiments are described that relate to failure determination for an integrated circuit. An integrated circuit can be tested to determine if the integrated circuit is functioning properly. The integrated circuit can be subjected to a specific radiation such that the integrated circuit produces a response. This response can be compared against an expected response to determine if the response matches the expected response. If the response does not match the expected response, then the integrated circuit fails the test. If the response matches the expected response, then the integrated circuit passes the test.

The disclosure describes a process and apparatus for accessing devices on a substrate. The substrate may include only full pin JTAG devices (504), only reduced pin JTAG devices (506), or a mixture of both full pin and reduced pin JTAG devices. The access is accomplished using a single interface (502) between the substrate (408) and a JTAG controller (404). The access interface may be a wired interface or a wireless interface and may be used for JTAG based device testing, debugging, programming, or other type of JTAG based operation.