The systems and methods described herein are for remaining useful life prediction in electronics and include measuring a plurality of circuit parameters for each of a plurality of circuit components at a plurality of different temperatures, determining a probability density function of failure as a function of time for each of the plurality of circuit components and combining the probability density functions for each of the plurality of circuit components as a function of a circuit that contains the plurality of circuit components.

Provided is a test method of a semiconductor device under test, the test method comprising: controlling the semiconductor device under test to an on state by inputting a control signal to the semiconductor device under test; and observing the semiconductor device under test at a time of controlling the semiconductor device under test in the on state to an off state and evaluating the semiconductor device under test, wherein the semiconductor device under test includes one semiconductor device under test or a plurality of semiconductor devices under test, and in the controlling to the on state, a length of an on-time for which the one semiconductor device under test or the plurality of semiconductor devices under test are set to the on state is adjusted based on a magnitude of a variation in a delay time of the control signal.

A switching arrangement of an inverter with a filter circuit and a grid relay. For the filter circuit use is made of an equivalent circuit consisting of effective filter inductance, from filter inductance and topology of the filter circuit and effective filter capacitance, from the filter capacitance and topology of the filter circuit. The effective filter inductance and the effective filter capacitance are system parameters. To determine system parameters, a voltage pulse is applied between a first conductor output and a second conductor output when the grid relay is open; the first conductor output and the second conductor output are connected via the switching arrangement to form a closed oscillating circuit a current value of the effective filter inductance and the effective filter capacitance is determined from a current curve and/or voltage curve in the resonant circuit as system parameters for controlling the switching arrangement.

A method for measuring (and controlling) a characteristic performance parameter Γ.sub.s of a device under test (DUT) having an input port (at the minimum). The method involves connecting the input port of the DUT to a signal generator, subjecting the DUT to a large signal input test signal, and executing a first measurement of the incident wave and reflected wave at a DUT input reference plane. The method further involves subjecting the DUT to a perturbation signal combined with the large signal input test signal, and executing a second measurement of the incident wave and reflected wave at the DUT input reference plane, and determining the characteristic performance parameter from the first measurement and the second measurement.

A system for monitoring a circuit, comprising a device under test, such as a power field effect transistor or capacitor, coupled to a power source and a signal source and configured to generate a power output using the signal source, a current output, a voltage output and an end of life detector coupled to the current output and the voltage output and configured to generate a first impedance as a function of the current output and the voltage output, to compare the first impedance to a second impedance and to generate an indicator if the first impedance exceeds the second impedance.

An exemplary embodiment of the present inventive concept provides a display device including: a display area where an image is displayed; a peripheral area disposed outside the display area; a hole area disposed within the display area; a hole crack detection line disposed adjacent to the hole area to surround the hole area and having a first end and a second end that is separated from the first end; a first detection line extending from the peripheral area and connected to the hole crack detection line to constitute a first closed circuit; a second detection line extending from the peripheral area and connected to the hole crack detection line to constitute a second closed circuit; and a circuit portion connected to the first detection line and the second detection line.

An artificial intelligence (AI)-based constrained random verification (CRV) method for a design under test (DUT) includes: receiving a series of constraints; obtaining a limited constraint range according to the series of constraints; generating a series of stimuli according to the limited constraint range; and verifying the DUT by the series of stimuli; wherein at least one of the step of obtaining the limited constraint range according to the series of constraints and the step of generating the series of stimuli according to the limited constraint range employs an AI algorithm.

An electrostatic encoder (40) detects the rotation angle of a rotor (42) with great accuracy based on the change in the capacitance between electrodes arranged on a stator (41) and the rotor (42). Detection electrodes (44a to 44d) and transmission electrodes (45a to 45d) are arranged circumferentially and alternately on the stator (41). Detection signals (phase A, phase B) amplitude-modulated based on the rotation of the rotor (42) and having a mutual phase difference of 90 degrees are output from adjacent ones of the detection electrodes. Modulated signals (V1, V2) are generated by demodulating the detection signals having a mutual phase difference of 90 degrees. Applying resolver-digital (RD) conversion processing to the modulated signals allows obtaining the rotation angle of the rotor.

A semiconductor inspection device includes: a measuring device that supplies power to a semiconductor device and measures the electrical characteristics; an optical scanning device that scans the semiconductor device with light intensity-modulated with a plurality of frequencies; a lock-in amplifier that acquires a characteristic signal indicating the electrical characteristics of the plurality of frequency components; and an inspection device that calculates a frequency at which the characteristic signal reflecting the electrical characteristics of a first layer and the characteristic signal reflecting the electrical characteristics of a second layer have a predetermined phase difference, corrects a phase component of the characteristic signal at an arbitrary scanning position with a phase component at the scanning position reflecting the electrical characteristics of the first layer as a reference, and outputs an in-phase component and a quadrature component at the arbitrary scanning position at the calculated frequency.

Methods and systems for authenticating electronic devices via multi tone analysis. A method for authenticating a device under test (DUT) of a type of DUT includes imparting voltage tones to the DUT. The voltage tones are proximate a frequency of interest that is associated with the type of DUT. Using a measurement response of the DUT to the voltage tones, an electronic signature of the DUT is determined. The DUT is determined to be authentic when the electronic signature of the DUT substantially matches an electronic signature of an authority DUT of the type of DUT.