Presented herein are techniques in which a software-controlled load is embedded at an output of a point of load (POL) in parallel to a load that receives power from the POL. A small incremental load is applied to the POL using the software-controlled load. A transient response of the POL to the applied small incremental load is measured using an embedded analysis functionality.

A system and method for detecting a failure in a redundant signal path during operation of the redundant path is disclosed. A test signal is sequentially injected into each signal path while an input signal is conducted by the other signal path not receiving the test signal. The test signal is selected at a frequency to verify operation of a filter connected in series along each path. A processor generates the test signal, injects the test signal at the input of the filter, and receives the output of the filter. The processor then generates a frequency response of the filter in each signal path as a function of the output from the filter and of the original test signal. The frequency response obtained along each of the redundant signal paths is compared to each other to detect a failure of one of the filters present along the respective signal paths.

A system for inspecting or screening electrically powered device includes a signal generator inputting a preselected signal into the electrically powered device. There is also an antenna array positioned at a pre-determined distance above the electrically powered device. Apparatus collects RF energy emitted by the electrically powered device in response to input of said preselected signal. The signature of the collected RF energy is compared with an RF energy signature of a genuine part. The comparison determines one of a genuine or counterfeit condition of the electrically powered device.

The present invention provides a general four-port on-wafer high frequency de-embedding method. The method comprises: for each on-wafer de-embedding dummy, building a model considering the distributive nature of high frequency characteristics of the on-wafer de-embedding dummy; obtaining the intrinsic Y-parameter admittance matrix of said N on-wafer de-embedding dummies by calculation or simulation by using said models; and solving the equation set which the corresponding measurement and calculation or simulation data of said on-wafer de-embedding dummies satisfy for the elements of the related admittance matrices of the parasitic four-port network to be stripped in de-embedding and model parameters of models on which said calculation or simulation is based.

Spike safe floating current and voltage source (VI) containing a forced voltage amplifier in series with a selectable resistor. A method of providing a VI with forced current testing mode using a forced voltage amplifier in series with a selectable resistor. A method of providing a VI with forced voltage testing mode using a forced voltage amplifier in series with a selectable resistor. A method of measuring the on resistance of a device under test using a VI with a forced voltage amplifier in series with a selectable resistor. A method of measuring the breakdown of an input/output junction of a device under test using a VI with a forced voltage amplifier in series with a selectable resistor.

The present invention provides an electrostatic atomizer which can be inspected at low cost. The electrostatic atomizer includes: a PWM signal generating section (27) which generates a PWM signal for controlling a high voltage generating device (22); an identifying section (28) which identifies an on-time of a PWM signal during a certain time; and a reporting section (33) which causes a report to be sent out of the electrostatic atomizer in a case where the on-time identified by the identifying section (28) is larger than a certain value.

A method, including determining a change in an actuator impedance based on a change in an electrical property of a system of which the actuator is apart, and determining one or more system characteristics based on the change in the actuator impedance.

A process corner detection circuit based on a self-timing oscillation ring comprises a reset circuit (1), the self-timing oscillation ring (2), and a counting module (3). The self-timing oscillation ring (2) consists of m two-input Miller units and inverters, and a two-input AND gate, m being a positive integer greater than or equal to 3. The circuit can be used for detecting a process corner of a fabricated integrated circuit chip, and reflecting the process corner of the chip according to the number of oscillations of the self-timing oscillation ring (2). The number of oscillations of the self-timing oscillation ring (2) in different process corners is acquired by Hspice simulation before the chip tape-out, and the process corner of the chip after the chip tape-out can be determined according to the actually measured number of oscillations.

In a power supply system, a high-side (HS) insulated-gate bipolar transistor (IGBT) has a first collector, a first gate, and a first emitter. A low-side (LS) IGBT has a second collector coupled to the first emitter, a second gate, and a second emitter. A gate drive circuit is coupled to the first gate of the HS IGBT and the second gate of the LS IGBT. A control circuit is coupled to the gate drive circuit. The control circuit is configured to control the gate drive circuit for biasing the HS IGBT to a HS saturation, and determine a HS degradation of the HS IGBT based on a HS digitized gate voltage of the HS IGBT in the HS saturation.

In a test system that provides a high fidelity output signal, a transition driving circuit can selectively enable multiple, parallel current paths based on a desired voltage transition. The transition driving circuit can include a first switch configured to switch a first current path between an output node and a first current source/sink, and a second switch configured to switch a second current path between the output node and the first current source/sink. The transition driving circuit can include a control circuit that is configured to receive information about a desired voltage transition and, depending on a magnitude of the desired voltage transition, to selectively turn on one or both of the first and second switches to enable one or both of the first and second current paths to provide respective portions of the output signal from the first current source/sink to the output node of the test system.