An input sensor short-circuit inspection method including: setting an inspection frequency for detecting a short-circuit of an input sensor comprising a plurality of electrodes; driving the input sensor in an inspection mode at the set inspection frequency; and detecting the short-circuit of the input sensor based on a capacitance charged between adjacent electrodes among the plurality of electrodes of the input sensor in the inspection mode.

A keyboard with wire aging self-adaption, a self-adaption method for keyboard, an electronic computing device readable medium with a stored program, and an electronic computing device program product are provided. In the keyboard, a processor feeds a scanning signal to each scanning line in turn during a scanning round. In response to the conduction state of one of switching elements, the processor detects a return signal on the corresponding return line and selects one or more scanning lines as a testing line. During a first duration in which the testing line maintains the scanning signal, according to the time difference between the starting points of the first duration and the return signal and the response time parameter corresponding to the testing line that is stored in the memory, the processor determines whether to update the response time parameter corresponding to the testing line that is stored in the memory.

A switch system includes a bidirectional switch, a first gate driver circuit, a second gate driver circuit, a control unit, a first decision unit, and a second decision unit. The bidirectional switch includes a first source, a second source, a first gate, and a second gate. The first decision unit determines, based on a voltage at the first gate and a first threshold voltage, a state of the first gate in a first period in which a signal to turn OFF the first gate is output from the control unit to the first gate driver circuit. The second decision unit determines, based on a voltage at the second gate and a second threshold voltage, a state of the second gate in a second period in which a signal to turn OFF the second gate is output from the control unit to the second gate driver circuit.

A method and a system for diagnosing an open circuit (OC) fault of an insulated gate bipolar transistor (IGBT) of a T-type three-level (T.sup.23L) inverter under multiple power factors based on instantaneous current distortion are provided. Similar characteristics of current distortion may be caused by an OC fault of a T.sup.23L inverter, making it is difficult to locate the fault. The method for diagnosing an OC fault of a grid-connected T.sup.23L inverter, can diagnose the OC fault hierarchically; four switch transistors in a phase can be divided into two groups according to the similarity analysis of current distortion under different power factors; group-based fault diagnosis is realized by half cycles in which a zero domain occurs; and then, a specific switching signal is injected to realize equipment-based OC fault diagnosis. The OC fault diagnosis of a T.sup.23L inverter is realized without additional hardware circuits.

Disclosed is a system and method for monitoring a characteristic of an environment of an electronic device. The electronic device may include a printed circuit board and a component. A sensor is placed on the printed circuit board, and may be between the component and the board, and connects to a monitor, or detector. An end user device may be used to store, assess, display and understand the data received from the sensor through the monitor.

A circuit architecture for expanded design for testability functionality is provided that includes an Intellectual Property (IP) core for use with a design for an integrated circuit (IC). The IP core provides an infrastructure harness circuit configured to control expanded design for testability functions available within the IC. An instance of the IP core can be included in a circuit block of the design for the IC. The infrastructure harness circuit can include an outward facing interface configured to connect to circuitry outside of the circuit block and an inward facing interface configured to connect to circuitry within the circuit block. The instance of the IP core can be parameterized to configure the infrastructure harness circuit to control a plurality of functions selected from the expanded design for testability functions based on a user parameterization of the instance of the IP core.

A display panel and a manufacturing method thereof are provided. The display panel includes a substrate, and a first connecting line, a second connecting line, a first GOA circuit, and a second GOA circuit disposed on the substrate. The first GOA circuit is disposed opposite to the second GOA circuit, and a first single-sided driving area and a second single-sided driving area are sequentially disposed between the first GOA circuit and the second GOA circuit. The first connecting line is disposed in the first single-sided driving area and connected to an input terminal of the first GOA circuit, and the second connecting line is disposed in the second single-sided driving area and connected to an input terminal of the second GOA circuit. The present disclosure can prevent screen tearing which is caused by single-sided driving when performing an aging test, and improve a yield of the display panel.

A system-on-chip (SoC) includes multiple critical components and a testing system to test the critical components. The critical components include an intellectual property (IP) core and an associated logic circuit. The testing system includes a controller, a fault injector, and a masking circuit. The controller is configured to receive a test initiation request and generate first and second select instructions. The fault injector is configured to generate and inject a set of fault inputs in the logic circuit based on the first select instruction to test the associated logic circuit and the IP core. The IP core is configured to generate a set of responses that is associated with the testing of the logic circuit and the associated IP core. The masking circuit is configured to mask and output the set of responses when the second select instruction indicates a first value and a second value, respectively.

According to one embodiment, an electronic circuit includes: a current supply circuit, a detection circuit, a timing generation circuit, a sample hold circuit and a calculation circuit. The current supply circuit supplies a sine wave current for measurement to a gate terminal of a semiconductor switching device. The detection circuit detects a sine wave voltage generated in response to supply of the sine wave current to generate a detection signal. The timing generation circuit counts cycles of the sine wave voltage. The sample hold circuit samples the detection signal at a timing depending on a count value of the timing generation circuit. The calculation circuit calculates a gate resistance of the semiconductor switching device based on the sampled voltage.

This disclosure proposes an inventive system capable of testing a component in the system during runtime. The system may comprise: a substrate; a plurality of functional components, of the plurality of functional components being mounted onto the substrate and including a circuitry; a system bus formed with electrically conductive pattern onto the substrate thereby allowing the plurality of functional components to communicate with each other; one or more wrappers, each of the one or more wrappers connected to one of the plurality of functional components; and an in-system component tester (ICT) configured to: select, as a component under test (CUT), at least one functional component, in an idle state, of the plurality of the functional components; and test, via the one or more test wrappers, the at least one functional component selected as the CUT.